1
0
mirror of synced 2026-02-16 21:10:58 +00:00
Files
YosysHQ.yosys/docs
Krystine Sherwin 742ec78ca3 Switching example synth to fifo
Fifo code based on SBY quick start.
Instead of showing the full design we are (currently) focusing on a single output (rdata), using `%ci*` to get the subcircuit it relies on.
2023-12-18 13:19:01 +13:00
..
2023-12-18 13:19:01 +13:00
2023-08-14 12:13:29 +12:00
2022-11-15 12:55:22 +01:00