This website requires JavaScript.
Explore
Help
Register
Sign In
github.com
/
YosysHQ.yosys
Watch
1
Star
0
Fork
0
You've already forked YosysHQ.yosys
mirror of
synced
2026-02-12 19:27:12 +00:00
Code
Issues
Releases
Wiki
Activity
Files
763401fc827d444bfef5a10ff658a3bf7e89b76c
YosysHQ.yosys
/
tests
/
arch
History
whitequark
763401fc82
ecp5: do not map FFRAM if explicitly requested otherwise.
2020-04-03 05:51:40 +00:00
..
anlogic
Call equiv_opt with -multiclock and -assert
2019-12-31 18:39:32 -08:00
common
ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
2020-02-06 16:52:51 +00:00
ecp5
ecp5: do not map FFRAM if explicitly requested otherwise.
2020-04-03 05:51:40 +00:00
efinix
Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
2020-02-05 10:47:31 -08:00
gowin
Add opt_lut_ins pass. (
#1673
)
2020-02-03 14:57:17 +01:00
ice40
ice40: do not map FFRAM if explicitly requested otherwise.
2020-04-03 05:51:40 +00:00
xilinx
abc9_ops: -reintegrate to use derived_type for box_ports
2020-02-05 14:46:48 -08:00
run-test.sh
Add simcells.v, simlib.v, and some output
2019-06-27 11:13:49 -07:00
