Clifford Wolf 9b183539af Implemented dynamic bit-/part-select for memory writes

2014-07-17 16:49:23 +02:00

..

.gitignore

added more .gitignore files (make test)

2013-01-05 11:35:52 +01:00

aes_kexp128.v

initial import

2013-01-05 11:13:26 +01:00

always01.v

Added test cases from 2012 paper on comparison of foss verilog synthesis tools

2013-03-31 11:17:56 +02:00

always02.v

Added test cases from 2012 paper on comparison of foss verilog synthesis tools

2013-03-31 11:17:56 +02:00

always03.v

Added test cases from 2012 paper on comparison of foss verilog synthesis tools

2013-03-31 11:17:56 +02:00

arraycells.v

added tests for new verilog features

2014-06-07 12:26:11 +02:00

arrays01.v

Added test cases from 2012 paper on comparison of foss verilog synthesis tools

2013-03-31 11:17:56 +02:00

carryadd.v

Bugfix in name resolution with generate blocks

2014-01-30 15:01:28 +01:00

constpower.v

Fixed handling of power operator

2013-11-07 22:20:00 +01:00

dff_different_styles.v

Added support for complex set-reset flip-flops in proc_dff

2013-10-24 16:54:05 +02:00

fiedler-cooley.v

initial import

2013-01-05 11:13:26 +01:00

forgen01.v

Progress in Verific bindings

2014-03-17 01:56:00 +01:00

forgen02.v

Added test cases from 2012 paper on comparison of foss verilog synthesis tools

2013-03-31 11:17:56 +02:00

fsm.v

initial import

2013-01-05 11:13:26 +01:00

generate.v

Various improvements in support for generate statements

2013-12-04 21:06:54 +01:00

hierarchy.v

Implemented correct handling of signed module parameters

2013-11-24 17:17:21 +01:00

i2c_master_tests.v

initial import

2013-01-05 11:13:26 +01:00

loops.v

initial import

2013-01-05 11:13:26 +01:00

macros.v

fixed parsing of constant with comment between size and value

2014-07-02 06:27:04 +02:00

mem2reg.v

Added test case for AstNode::MEM2REG_FL_CMPLX_LHS

2014-06-17 21:49:59 +02:00

mem_arst.v

Progress in Verific bindings

2014-03-17 01:56:00 +01:00

memory.v

Implemented dynamic bit-/part-select for memory writes

2014-07-17 16:49:23 +02:00

multiplier.v

Added multiplier test case from eda playground

2013-12-18 13:43:53 +01:00

muxtree.v

Fixed parsing of default cases when not last case

2013-11-18 16:10:50 +01:00

omsp_dbg_uart.v

initial import

2013-01-05 11:13:26 +01:00

operators.v

Added support for "2**n" shifter encoding

2013-08-12 14:47:50 +02:00

paramods.v

Added defparam support to Verilog/AST frontend

2013-07-04 14:12:33 +02:00

partsel.v

Implemented indexed part selects

2013-11-20 13:05:27 +01:00

process.v

Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values

2013-04-13 21:19:10 +02:00

realexpr.v

Fixed handling of mixed real/int ternary expressions

2014-06-25 10:05:36 +02:00

repwhile.v

added tests for new verilog features

2014-06-07 12:26:11 +02:00

rotate.v

Another name resolution bugfix for generate blocks

2013-11-20 13:57:40 +01:00

run-test.sh

Added note to "make test": use git checkout of iverilog

2014-07-16 10:03:07 +02:00

signedexpr.v

Major redesign of expr width/sign detecion (verilog/ast frontend)

2013-07-09 14:31:57 +02:00

sincos.v

Fix in sincos testbench gen

2013-12-04 09:24:52 +01:00

subbytes.v

initial import

2013-01-05 11:13:26 +01:00

task_func.v

initial import

2013-01-05 11:13:26 +01:00

undef_eqx_nex.v

Added proper === and !== support in constant expressions

2013-12-27 13:50:08 +01:00

usb_phy_tetsts.v

initial import

2013-01-05 11:13:26 +01:00

values.v

Replaced RTLIL::Const::str with generic decoder method

2013-12-04 14:14:05 +01:00

vloghammer.v

Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing before constfold fixes)

2013-11-02 21:13:01 +01:00