This website requires JavaScript.
Explore
Help
Register
Sign In
github.com
/
YosysHQ.yosys
Watch
1
Star
0
Fork
0
You've already forked YosysHQ.yosys
mirror of
synced
2026-05-03 14:50:26 +00:00
Code
Issues
Releases
Wiki
Activity
Files
7bbdf6049aeced309a2fe7e10f2f60b6cd7dd596
YosysHQ.yosys
/
techlibs
/
ecp5
/
cells_sim.v
gatecat
266f81816b
ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model
...
Signed-off-by: gatecat <
gatecat@ds0.me
>
2023-04-06 10:18:48 +01:00
22 KiB
Raw
Blame
History
View Raw
Reference in New Issue
View Git Blame
Copy Permalink