github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-05 07:35:21 +00:00
Code Issues Releases Wiki Activity
Files
7bd2144d03ae5daffbcddea609d2db7df7b751a2
YosysHQ.yosys/techlibs/xilinx/cells_xtra.v
Clifford Wolf 5f1fea08d5 Add inout ports to cells_xtra.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-04 11:30:55 +02:00

99 KiB
Raw Blame History

View Raw
Reference in New Issue View Git Blame Copy Permalink