github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-05 07:35:21 +00:00
Code Issues Releases Wiki Activity
Files
7e6426a67da352e0ea41f80b9303087545cb12ac
YosysHQ.yosys/passes/techmap/abc.cc
Clifford Wolf 17372d8abd Added "abc -luts" option, Improved Xilinx logic mapping
2016-02-01 12:40:32 +01:00

56 KiB
Raw Blame History

View Raw
Reference in New Issue View Git Blame Copy Permalink