YosysHQ.yosys/tests/verilog/include_self.v at 8e331b7795c05599784bf60cecbbb487c3f00a45

mirror of synced 2026-02-21 07:05:05 +00:00

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Zachary Snow 1ec5994100 verilog: fix handling of nested ifdef directives

- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else

2021-03-01 12:28:33 -05:00

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