This website requires JavaScript.
Explore
Help
Register
Sign In
github.com
/
YosysHQ.yosys
Watch
1
Star
0
Fork
0
You've already forked YosysHQ.yosys
mirror of
synced
2026-05-04 23:27:07 +00:00
Code
Issues
Releases
Wiki
Activity
Files
983479f395ca2edade4d538a225a3426a1fcff38
YosysHQ.yosys
/
techlibs
/
intel
/
synth_intel.cc
Clifford Wolf
65f91e5120
Rename "write_verilog -nobasenradix" to "write_verilog -decimal"
2017-10-03 17:31:21 +02:00
8.0 KiB
Executable File
Raw
Blame
History
View Raw
Reference in New Issue
View Git Blame
Copy Permalink