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YosysHQ.yosys/kernel/register.cc
Krystine Sherwin a2b2904ed8 cellhelp: Add source line to help
Include Source file and line number in SimHelper struct, and use it for verilog code caption in rst dump.
Also reformat python string conversion to iterate over a list of fields instead of repeating code for each.
2024-10-15 07:16:40 +13:00

32 KiB