1
0
mirror of synced 2026-02-09 01:50:59 +00:00
Files
YosysHQ.yosys/techlibs/anlogic/eagle_bb.v
Icenowy Zheng 634d7d1c14 Revert "Leave only real black box cells"
This reverts commit 43030db5ff.

For a synthesis tool, generating EG_LOGIC cells are a good choice, as
they can be furtherly optimized when PnR, although sometimes EG_LOGIC is
not as blackbox as EG_PHY cells (because the latter is more close to the
hardware implementation).

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-17 23:20:40 +08:00

33 KiB