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b454735bea6727f346fdbbc28f261b40d91c61ba
YosysHQ.yosys
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tests
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svinterfaces
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svinterface1_tb.v
Ruben Undheim
d5aac2650f
Basic test for checking correct synthesis of SystemVerilog interfaces
2018-10-18 22:40:53 +02:00
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