Xiretza 092e923330 verilog: fix buf/not primitives with multiple outputs ...

From IEEE1364-2005, section 7.3 buf and not gates:

> These two logic gates shall have one input and one or more outputs.
> The last terminal in the terminal list shall connect to the input of the
> logic gate, and the other terminals shall connect to the outputs of
> the logic gate.

yosys does not follow this and instead interprets the first argument as
the output, the second as the input and ignores the rest.

2021-03-17 11:44:03 -04:00

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.gitignore

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aes_kexp128.v

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always01.v

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always02.v

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always03.v

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arraycells.v

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arrays01.v

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arrays02.sv

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attrib01_module.v

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attrib02_port_decl.v

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attrib03_parameter.v

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attrib04_net_var.v

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attrib05_port_conn.v.DISABLED

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attrib06_operator_suffix.v

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attrib07_func_call.v.DISABLED

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attrib08_mod_inst.v

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attrib09_case.v

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carryadd.v

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const_branch_finish.v

Fix begin/end in generate

2020-11-11 12:03:37 +09:00

const_fold_func.v

verilog: refactored constant function evaluation

2021-02-04 10:18:27 -05:00

const_func_shadow.v

verilog: refactored constant function evaluation

2021-02-04 10:18:27 -05:00

constmuldivmod.v

Expand tests/simple/constmuldivmod.v

2020-05-28 22:59:04 +02:00

constpower.v

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defvalue.sv

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dff_different_styles.v

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dff_init.v

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dynslice.v

Add dynamic slicing Verilog testcase

2020-03-31 11:51:31 -07:00

fiedler-cooley.v

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forgen01.v

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forgen02.v

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forloops.v

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fsm.v

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func_block.v

verilog: significant block scoping improvements

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func_recurse.v

verilog: significant block scoping improvements

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func_width_scope.v

verilog: significant block scoping improvements

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genblk_collide.v

verilog: significant block scoping improvements

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genblk_dive.v

verilog: significant block scoping improvements

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genblk_order.v

verilog: significant block scoping improvements

2021-01-31 09:42:09 -05:00

genblk_port_shadow.v

verlog: allow shadowing module ports within generate blocks

2021-02-07 11:48:39 -05:00

generate.v

Merge pull request #2529 from zachjs/unnamed-genblk

2021-02-04 09:57:28 +00:00

graphtest.v

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hierarchy.v

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hierdefparam.v

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i2c_master_tests.v

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ifdef_1.v

verilog: fix handling of nested ifdef directives

2021-03-01 12:28:33 -05:00

ifdef_2.v

verilog: fix handling of nested ifdef directives

2021-03-01 12:28:33 -05:00

implicit_ports.v

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local_loop_var.sv

verilog: significant block scoping improvements

2021-01-31 09:42:09 -05:00

localparam_attr.v

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loop_var_shadow.v

verilog: significant block scoping improvements

2021-01-31 09:42:09 -05:00

loops.v

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macro_arg_spaces.sv

verilog: allow spaces in macro arguments

2021-01-20 08:49:58 -07:00

macro_arg_surrounding_spaces.v

verilog: strip leading and trailing spaces in macro args

2021-01-28 11:26:35 -05:00

macros.v

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mem2reg.v

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mem_arst.v

Make SV2017 compliant courtesy of @wsnyder

2019-12-12 07:34:07 -08:00

memory.v

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module_scope.v

verilog: support module scope identifiers in parametric modules

2021-03-16 11:01:30 -04:00

multiplier.v

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muxtree.v

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named_genblk.v

verilog: significant block scoping improvements

2021-01-31 09:42:09 -05:00

nested_genblk_resolve.v

verilog: significant block scoping improvements

2021-01-31 09:42:09 -05:00

omsp_dbg_uart.v

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operators.v

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param_attr.v

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paramods.v

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partsel.v

Bugfix in partsel.v signed indices test cases

2020-05-02 11:21:01 +02:00

process.v

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realexpr.v

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repwhile.v

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retime.v

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rotate.v

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run-test.sh

tests/simple: remove "nullglob" shopt

2020-09-21 15:07:02 +02:00

scopes.v

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signedexpr.v

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sincos.v

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specify.v

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string_format.v

Allow %0s $display format specifier

2020-08-09 17:19:49 -04:00

subbytes.v

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task_func.v

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undef_eqx_nex.v

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unnamed_block_decl.sv

verilog: significant block scoping improvements

2021-01-31 09:42:09 -05:00

usb_phy_tests.v

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values.v

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verilog_primitives.v

verilog: fix buf/not primitives with multiple outputs

2021-03-17 11:44:03 -04:00

vloghammer.v

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wandwor.v

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wreduce.v

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xfirrtl

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