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YosysHQ.yosys/tests/verilog
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Emil J. Tywoniak 6042ae0e8a simplify: add smoke test for system function calls
2025-08-12 12:59:31 +02:00
..
.gitignore
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
absurd_width_const.ys
…
absurd_width.ys
…
always_comb_latch_1.ys
sv: auto add nosync to certain always_comb local vars
2022-01-07 22:53:22 -07:00
always_comb_latch_2.ys
sv: auto add nosync to certain always_comb local vars
2022-01-07 22:53:22 -07:00
always_comb_latch_3.ys
sv: auto add nosync to certain always_comb local vars
2022-01-07 22:53:22 -07:00
always_comb_latch_4.ys
sv: auto add nosync to certain always_comb local vars
2022-01-07 22:53:22 -07:00
always_comb_nolatch_1.ys
sv: auto add nosync to certain always_comb local vars
2022-01-07 22:53:22 -07:00
always_comb_nolatch_2.ys
sv: auto add nosync to certain always_comb local vars
2022-01-07 22:53:22 -07:00
always_comb_nolatch_3.ys
sv: auto add nosync to certain always_comb local vars
2022-01-07 22:53:22 -07:00
always_comb_nolatch_4.ys
sv: auto add nosync to certain always_comb local vars
2022-01-07 22:53:22 -07:00
always_comb_nolatch_5.ys
sv: fix always_comb auto nosync for nested and function blocks
2022-04-05 14:43:48 -06:00
always_comb_nolatch_6.ys
sv: fix always_comb auto nosync for nested and function blocks
2022-04-05 14:43:48 -06:00
asgn_expr_not_proc_1.ys
sv: support assignments within expressions
2023-09-05 22:27:55 -04:00
asgn_expr_not_proc_2.ys
sv: support assignments within expressions
2023-09-05 22:27:55 -04:00
asgn_expr_not_proc_3.ys
sv: support assignments within expressions
2023-09-05 22:27:55 -04:00
asgn_expr_not_proc_4.ys
sv: support assignments within expressions
2023-09-05 22:27:55 -04:00
asgn_expr_not_proc_5.ys
sv: support assignments within expressions
2023-09-05 22:27:55 -04:00
asgn_expr_not_sv_1.ys
sv: support assignments within expressions
2023-09-05 22:27:55 -04:00
asgn_expr_not_sv_2.ys
sv: support assignments within expressions
2023-09-05 22:27:55 -04:00
asgn_expr_not_sv_3.ys
sv: support assignments within expressions
2023-09-05 22:27:55 -04:00
asgn_expr_not_sv_4.ys
sv: support assignments within expressions
2023-09-05 22:27:55 -04:00
asgn_expr.sv
fix width of post-increment/decrement expressions
2023-09-18 23:46:06 -04:00
asgn_expr.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
assign_to_reg.ys
Remove references to ilang
2024-11-05 12:36:31 +13:00
atom_type_signedness.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
block_end_label_only.ys
…
block_end_label_wrong.ys
…
block_labels.ys
Standard compliance for tests/verilog/block_labels.ys
2023-05-21 16:38:14 -04:00
bug656.v
…
bug656.ys
…
bug2037.ys
…
bug2042-sv.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
bug2042.ys
…
bug2493.ys
…
bug4785.ys
simplify: Skip AST_PRIMITIVE in AST_CELLARRAY
2025-03-25 12:15:54 +13:00
conflict_assert.ys
…
conflict_cell_memory.ys
…
conflict_interface_port.ys
…
conflict_memory_wire.ys
…
conflict_pwire.ys
…
conflict_wire_memory.ys
…
const_arst.ys
…
const_sr.ys
…
constparser_f_file.sv
const2ast: add diagnostics tests
2025-06-16 21:48:12 +02:00
constparser_f_file.ys
const2ast: add diagnostics tests
2025-06-16 21:48:12 +02:00
constparser_f.ys
fixup! const2ast: add diagnostics tests
2025-06-16 22:50:31 +02:00
constparser_g.ys
const2ast: add diagnostics tests
2025-06-16 21:48:12 +02:00
delay_mintypmax.ys
…
delay_risefall.ys
…
delay_time_scale.ys
verilog: support for time scale delay values
2022-02-14 15:58:31 +01:00
doubleslash.ys
fixup verilog doubleslash test
2022-01-03 08:17:46 -07:00
dynamic_range_lhs.sh
Include x bits in test of lhs dynamic part-select
2024-01-10 20:28:36 +01:00
dynamic_range_lhs.v
Include x bits in test of lhs dynamic part-select
2024-01-10 20:28:36 +01:00
fcall_smoke.ys
simplify: add smoke test for system function calls
2025-08-12 12:59:31 +02:00
for_decl_no_init.ys
sv: support declaration in procedural for initialization
2021-08-30 15:19:21 -06:00
for_decl_no_sv.ys
sv: support declaration in procedural for initialization
2021-08-30 15:19:21 -06:00
for_decl_shadow.sv
sv: support declaration in procedural for initialization
2021-08-30 15:19:21 -06:00
for_decl_shadow.ys
sv: support declaration in procedural for initialization
2021-08-30 15:19:21 -06:00
func_arg_mismatch_1.ys
…
func_arg_mismatch_2.ys
…
func_arg_mismatch_3.ys
…
func_arg_mismatch_4.ys
…
func_task_arg_copying.ys
tests: add tests for task/function argument input/output copying
2025-05-31 01:21:06 +01:00
func_tern_hint.sv
verilog: fix width/sign detection for functions
2022-05-30 16:45:39 -04:00
func_tern_hint.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
func_typename_ret.sv
…
func_typename_ret.ys
…
func_upto.sv
verilog: fix const func eval with upto variables
2022-02-11 21:01:51 +01:00
func_upto.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
gen_block_end_label_only.ys
…
gen_block_end_label_wrong.ys
…
genblk_case.v
…
genblk_case.ys
…
genblk_port_decl.ys
…
genfor_decl_no_init.ys
sv: support declaration in generate for initialization
2021-08-31 12:34:55 -06:00
genfor_decl_no_sv.ys
sv: support declaration in generate for initialization
2021-08-31 12:34:55 -06:00
genvar_loop_decl_1.sv
sv: support declaration in generate for initialization
2021-08-31 12:34:55 -06:00
genvar_loop_decl_1.ys
sv: support declaration in generate for initialization
2021-08-31 12:34:55 -06:00
genvar_loop_decl_2.sv
sv: support declaration in generate for initialization
2021-08-31 12:34:55 -06:00
genvar_loop_decl_2.ys
sv: support declaration in generate for initialization
2021-08-31 12:34:55 -06:00
genvar_loop_decl_3.sv
sv: support declaration in generate for initialization
2021-08-31 12:34:55 -06:00
genvar_loop_decl_3.ys
sv: support declaration in generate for initialization
2021-08-31 12:34:55 -06:00
global_parameter.ys
…
hidden_decl.ys
…
ifdef_nest.ys
…
ifdef_unterminated.ys
…
incdec.ys
tests: add tests for verilog pre/post increment/decrement in expressions
2025-05-30 14:38:25 +01:00
include_self.v
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include_self.ys
…
int_types.sv
…
int_types.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
localparam_no_default_1.ys
…
localparam_no_default_2.ys
…
macro_arg_tromp.sv
verilog: save and restore overwritten macro arguments
2021-07-28 21:52:16 -04:00
macro_arg_tromp.ys
verilog: save and restore overwritten macro arguments
2021-07-28 21:52:16 -04:00
macro_unapplied_newline.ys
…
macro_unapplied.ys
…
mem_bounds.sv
…
mem_bounds.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
module_end_label.ys
…
net_types.sv
sv: support wand and wor of data types
2021-09-21 14:52:28 -04:00
net_types.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
package_end_label.ys
…
package_import_separate_module.sv
use more standard naming conventions
2025-08-06 15:39:30 -04:00
package_import_separate.sv
use more standard naming conventions
2025-08-06 15:39:30 -04:00
package_import_separate.ys
add newline - whitespace
2025-08-06 19:00:11 -04:00
package_task_func.sv
…
package_task_func.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
param_default.ys
tests: Add default param test file
2025-05-05 10:18:52 +12:00
param_int_types.sv
…
param_int_types.ys
…
param_no_default_not_svmode.ys
…
param_no_default_unbound_1.ys
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param_no_default_unbound_2.ys
…
param_no_default_unbound_3.ys
…
param_no_default_unbound_4.ys
…
param_no_default_unbound_5.ys
…
param_no_default.sv
…
param_no_default.ys
hierarchy: Without a known top module, derive all deferred modules
2024-02-06 10:31:40 +01:00
parameters_across_files.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
past_signedness.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
port_int_types.sv
…
port_int_types.ys
…
prefix.sv
verilog: fix multiple AST_PREFIX scope resolution issues
2021-09-21 12:10:59 -04:00
prefix.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
priority_if_enc.ys
Add semantic test cases for SystemVerilog priority/unique/unique0 "if".
2025-05-24 08:44:04 -06:00
roundtrip_proc.ys
Test roundtripping some processes to Verilog and back
2024-01-24 16:32:25 +00:00
run-test.sh
test: restore verific handling, nicer naming
2024-12-13 10:24:47 +01:00
sbvector.ys
verific: support single_bit_vector
2025-05-12 13:23:29 +02:00
sign_array_query.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
size_cast.sv
Added cast to type support (#4284)
2024-09-29 17:03:01 -04:00
size_cast.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
string-literals.ys
verilog: add support for SystemVerilog string literals.
2025-07-03 20:51:12 -06:00
struct_access.sv
Fix access to whole sub-structs (#3086)
2022-02-14 14:34:20 +01:00
struct_access.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
task_attr.ys
sv: support assignments within expressions
2023-09-05 22:27:55 -04:00
typedef_across_files.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
typedef_const_shadow.sv
Add test for typenames using constants shadowed later on
2023-02-12 17:03:37 -05:00
typedef_const_shadow.ys
Add test for typenames using constants shadowed later on
2023-02-12 17:03:37 -05:00
typedef_legacy_conflict.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
unbased_unsized_shift.sv
verilog: Fix const eval of unbased unsized constants
2023-04-20 12:12:50 +02:00
unbased_unsized_shift.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
unbased_unsized_tern.sv
verilog: use derived module info to elaborate cell connections
2021-10-25 18:25:50 -07:00
unbased_unsized_tern.ys
verilog: use derived module info to elaborate cell connections
2021-10-25 18:25:50 -07:00
unbased_unsized.sv
…
unbased_unsized.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
unique0_if_enc.ys
Add semantic test cases for SystemVerilog priority/unique/unique0 "if".
2025-05-24 08:44:04 -06:00
unique_if_else_begin.ys
Accept (and ignore) SystemVerilog unique/priority if.
2025-05-22 19:28:28 -06:00
unique_if_else.ys
Accept (and ignore) SystemVerilog unique/priority if.
2025-05-22 19:28:28 -06:00
unique_if_enc.ys
Add semantic test cases for SystemVerilog priority/unique/unique0 "if".
2025-05-24 08:44:04 -06:00
unique_if.ys
Accept (and ignore) SystemVerilog unique/priority if.
2025-05-22 19:28:28 -06:00
unique_priority_case.ys
tests: add cases covering full_case and parallel_case semantics
2025-05-29 20:45:57 -06:00
unique_priority_if.ys
tests: add cases covering full_case and parallel_case semantics
2025-05-29 20:45:57 -06:00
unmatched_else.ys
…
unmatched_elsif.ys
…
unmatched_endif_2.ys
…
unmatched_endif.ys
…
unnamed_block.ys
…
unnamed_genblk.sv
…
unnamed_genblk.ys
…
unreachable_case_sign.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
upto.ys
…
void_func.ys
verilog: Support void functions
2023-03-20 12:52:46 +01:00
wire_and_var.sv
…
wire_and_var.ys
…