github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-04-26 12:18:43 +00:00
Code Issues Releases Wiki Activity
Files
bc0df04e065d53f3f1e2053861a94de29eb9e013
YosysHQ.yosys/techlibs/ecp5/cells_sim.v
gatecat 266f81816b ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model 
Signed-off-by: gatecat <gatecat@ds0.me>
2023-04-06 10:18:48 +01:00

22 KiB
Raw Blame History

View Raw
Reference in New Issue View Git Blame Copy Permalink