Clifford Wolf 65f91e5120 Rename "write_verilog -nobasenradix" to "write_verilog -decimal"

2017-10-03 17:31:21 +02:00

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a10gx

Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now

2017-10-01 11:04:17 -05:00

common

Tested and working altsyncarm without init files

2017-10-01 19:59:45 -05:00

cycloneiv

Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now

2017-10-01 11:04:17 -05:00

cycloneive

Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now

2017-10-01 11:04:17 -05:00

cyclonev

Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now

2017-10-01 11:04:17 -05:00

max10

Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now

2017-10-01 11:04:17 -05:00

Makefile.inc

Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now

2017-10-01 11:04:17 -05:00

synth_intel.cc

Rename "write_verilog -nobasenradix" to "write_verilog -decimal"

2017-10-03 17:31:21 +02:00