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c10e96c9ec8c4e56935ba796af0fa3d1f22b2a71
YosysHQ.yosys
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techlibs
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intel
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common
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dh73
4718e65763
Tested and working altsyncarm without init files
2017-10-01 19:59:45 -05:00
..
altpll_bb.v
Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
2017-10-01 11:04:17 -05:00
brams_map.v
Tested and working altsyncarm without init files
2017-10-01 19:59:45 -05:00
brams.txt
Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
2017-10-01 11:04:17 -05:00
m9k_bb.v
Tested and working altsyncarm without init files
2017-10-01 19:59:45 -05:00