github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-05 15:45:07 +00:00
Code Issues Releases Wiki Activity
Files
c3d4bb4cc95c417225fec8b16147dec3453ab94d
YosysHQ.yosys/techlibs/common/simlib.v
Marcelina Kościelnicka fd79217763 Add v2 memory cells.
2021-08-11 13:34:10 +02:00

59 KiB
Raw Blame History

View Raw
Reference in New Issue View Git Blame Copy Permalink