github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-25 08:31:37 +00:00
Code Issues Releases Wiki Activity
Files
c6fa4faa371ad3dbefe4c57bd758942e461869da
YosysHQ.yosys/kernel/rtlil.cc
Clifford Wolf 287de4b848 Add rewrite_sigspecs2, Improve remove() wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-15 16:01:00 +02:00

106 KiB
Raw Blame History

View Raw
Reference in New Issue View Git Blame Copy Permalink