Charlotte 7f7c61c9f0 fmt: remove lzero by lowering during Verilog parse ...

See https://github.com/YosysHQ/yosys/pull/3721#issuecomment-1502037466
-- this reduces logic within the cell, and makes the rules that apply
much more clear.

2023-08-11 04:46:52 +02:00

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