Clifford Wolf 70d7a02cae Added support for hierarchical defparams

2016-11-15 13:35:19 +01:00

..

.gitignore

…

aes_kexp128.v

…

always01.v

…

always02.v

…

always03.v

…

arraycells.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

arrays01.v

…

carryadd.v

…

constmuldivmod.v

Added opt_expr support for div/mod by power-of-two

2016-05-29 12:17:36 +02:00

constpower.v

…

dff_different_styles.v

Another block of spelling fixes

2015-08-14 23:27:05 +02:00

fiedler-cooley.v

…

forgen01.v

…

forgen02.v

…

fsm.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

generate.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

graphtest.v

Added tests/simple/graphtest.v

2015-11-30 11:41:12 +01:00

hierarchy.v

Another block of spelling fixes

2015-08-14 23:27:05 +02:00

hierdefparam.v

Added support for hierarchical defparams

2016-11-15 13:35:19 +01:00

i2c_master_tests.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

loops.v

Fixed trailing whitespaces

2015-07-02 11:14:30 +02:00

macros.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

mem2reg.v

Added another mem2reg test case

2016-08-21 13:45:46 +02:00

mem_arst.v

…

memory.v

Fixed bug with memories that do not have a down-to-zero data width

2016-08-22 14:27:46 +02:00

multiplier.v

…

muxtree.v

improvements in muxtree/select_leaves test

2015-01-18 13:24:01 +01:00

omsp_dbg_uart.v

Fixed trailing whitespaces

2015-07-02 11:14:30 +02:00

operators.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

paramods.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

partsel.v

Added support for "upto" wires to Verilog front- and back-end

2014-07-28 14:25:03 +02:00

process.v

…

realexpr.v

…

repwhile.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

rotate.v

Another block of spelling fixes

2015-08-14 23:27:05 +02:00

run-test.sh

Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.

2016-09-22 11:49:29 -06:00

scopes.v

Improved scope resolution of local regs in Verilog+AST frontend

2014-08-05 12:15:53 +02:00

signedexpr.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

sincos.v

…

subbytes.v

…

task_func.v

More bugfixes in handling of parameters in tasks and functions

2015-11-12 13:02:36 +01:00

undef_eqx_nex.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

usb_phy_tests.v

Renamed some of the test cases in tests/simple to avoid name collisions

2014-07-25 13:01:45 +02:00

values.v

…

vloghammer.v

Another block of spelling fixes

2015-08-14 23:27:05 +02:00

wreduce.v

Improvements in wreduce

2015-10-31 13:39:30 +01:00