Clifford Wolf c8305e3a6d Fixed a bug with autowire bit size ...

(removed leftover from when we tried to auto-size the wires)

2015-02-08 00:48:23 +01:00

..

ast

Fixed a bug with autowire bit size

2015-02-08 00:48:23 +01:00

ilang

Enable bison to be customized

2015-01-08 09:56:20 -02:00

liberty

namespace Yosys

2014-09-27 16:17:53 +02:00

verific

Added log_warning() API

2014-11-09 10:44:23 +01:00

verilog

Ignoring more system task and functions

2015-01-15 13:08:19 +01:00

vhdl2verilog

Header changes so it will compile on VS

2014-10-17 11:41:36 +02:00