Clifford Wolf c8305e3a6d Fixed a bug with autowire bit size ...

(removed leftover from when we tried to auto-size the wires)

2015-02-08 00:48:23 +01:00

..

ast.cc

Added global yosys_celltypes

2014-12-29 14:30:33 +01:00

ast.h

dict/pool changes in ast

2014-12-29 03:11:50 +01:00

dpicall.cc

Renamed SIZE() to GetSize() because of name collision on Win32

2014-10-10 17:07:24 +02:00

genrtlil.cc

Fixed a bug with autowire bit size

2015-02-08 00:48:23 +01:00

Makefile.inc

Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)

2014-08-21 12:43:51 +02:00

simplify.cc

Added ENABLE_NDEBUG makefile options

2015-01-24 12:16:46 +01:00