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YosysHQ.yosys/Makefile
Krystine Sherwin d7248303c6 analogdevices: Extra tests
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
2025-11-12 22:44:12 +00:00

42 KiB