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cb03a1ec2121cde499253c8f3738bac8fdb400b0
YosysHQ.yosys
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tests
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svinterfaces
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svinterface1.sv
Ruben Undheim
d5aac2650f
Basic test for checking correct synthesis of SystemVerilog interfaces
2018-10-18 22:40:53 +02:00
2.5 KiB
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