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YosysHQ.yosys/tests/verilog/.gitignore
Krystine Sherwin 9a09758f56 Test empty switches
2026-01-07 13:21:33 +13:00

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/bug5572.v
/const_arst.v
/const_sr.v
/doubleslash.v
/reset_auto_counter.v
/roundtrip_proc_1.v
/roundtrip_proc_2.v
/assign_to_reg.v
/subdir
/temp_foo.v