This website requires JavaScript.
Explore
Help
Register
Sign In
github.com
/
YosysHQ.yosys
Watch
1
Star
0
Fork
0
You've already forked YosysHQ.yosys
mirror of
synced
2026-04-30 05:36:39 +00:00
Code
Issues
Releases
Wiki
Activity
Files
cd12f2ddcfbdbfbf147afc2c90ddc54ec1f74485
YosysHQ.yosys
/
frontends
/
verilog
History
Stefan Biereigel
fd003e0e97
fix indentation across files
2019-05-23 13:57:27 +02:00
..
.gitignore
Add "make coverage"
2018-08-27 14:22:21 +02:00
const2ast.cc
Convert more log_error() to log_file_error() where possible.
2018-07-20 09:37:44 -07:00
Makefile.inc
Read bigger Verilog files.
2019-05-18 14:20:30 +03:00
preproc.cc
Support SystemVerilog `` extension for macros
2018-05-17 00:09:56 -04:00
verilog_frontend.cc
Merge remote-tracking branch 'origin/master' into clifford/specify
2019-05-03 15:05:57 -07:00
verilog_frontend.h
Add specify parser
2019-04-23 21:36:59 +02:00
verilog_lexer.l
make lexer/parser aware of wand/wor net types
2019-05-23 13:57:27 +02:00
verilog_parser.y
fix indentation across files
2019-05-23 13:57:27 +02:00