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YosysHQ.yosys/backends/firrtl/test.sh
Adam Izraelevitz 794cec0016 More progress on Firrtl backend.
Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a
simple rocket-chip design.
2017-02-13 11:17:53 -08:00

395 B