1
0
mirror of synced 2026-05-05 07:35:21 +00:00
Files
YosysHQ.yosys/techlibs/xilinx/xc7_dsp_map.v
Eddie Hung de79978372 xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)
* xilinx: eliminate SCCs from DSP48E1 model

* xilinx: add SCC test for DSP48E1

* Update techlibs/xilinx/cells_sim.v

* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1

Have a test that checks it works through ABC9 when enabled
2020-09-23 09:15:24 -07:00

884 B