YosysHQ.yosys/intel at eab3272cdeed697bdb9664c2d8a133d336addb7c - YosysHQ.yosys - Berget Git Service

github.com/YosysHQ.yosys

mirror of synced 2026-01-13 15:37:16 +00:00

History

Dan Ravensloft eab3272cde synth_intel: cyclone10 -> cyclone10lp

2019-12-10 13:47:58 +00:00

..

Clean whitespace and permissions in techlibs/intel

2017-10-05 16:23:49 +02:00

intel: Map M9K BRAM only on families that have it

2019-07-23 18:11:11 +01:00

synth_intel: cyclone10 -> cyclone10lp

2019-12-10 13:47:58 +00:00

Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device

2018-03-31 22:48:47 -06:00

Reduce amount of trailing whitespace in code base

2019-02-28 14:58:11 -08:00

Fixing issues in CycloneV cell sim

2019-04-11 19:59:03 -05:00

Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device

2018-03-31 22:48:47 -06:00

Makefile.inc

synth_intel: cyclone10 -> cyclone10lp

2019-12-10 13:47:58 +00:00

synth_intel.cc

synth_intel: cyclone10 -> cyclone10lp

2019-12-10 13:47:58 +00:00