Dan Ravensloft eab3272cde synth_intel: cyclone10 -> cyclone10lp

2019-12-10 13:47:58 +00:00

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achronix

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anlogic

make note that it is for latch mode

2019-09-18 17:48:16 +02:00

common

Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp

2019-11-11 15:07:29 +01:00

coolrunner2

coolrunner2: remove spurious log_pop() call, fixes #1463

2019-11-23 06:21:40 +01:00

easic

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ecp5

ecp5: Use new autoname pass for better cell/net names

2019-11-15 21:03:11 +00:00

efinix

FF should be initialized to 0

2019-10-04 13:27:10 +02:00

gowin

Use -match-init to not synth contradicting init values

2019-12-03 15:12:25 +01:00

greenpak4

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ice40

Merge pull request #1490 from YosysHQ/clifford/autoname

2019-11-14 18:03:44 +01:00

intel

synth_intel: cyclone10 -> cyclone10lp

2019-12-10 13:47:58 +00:00

sf2

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xilinx

xilinx: Add tristate buffer mapping. (#1528)

2019-12-04 09:44:00 +01:00

.gitignore

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