Gary Wong 7b09dc31af tests: add cases covering full_case and parallel_case semantics ...

This is @KrystalDelusion's suggestion in PR #5141 to verify
sensible implementation of all 4 possible full_case/parallel_case
combinations.

(Also including two similar tests to check the Verilog frontend
applies the correct attributes when given SystemVerilog
priority/unique case and if statements.)

2025-05-29 20:45:57 -06:00

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