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YosysHQ.yosys/tests/verilog/conflict_pwire.ys
2021-02-26 18:08:23 -05:00

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logger -expect error "Cannot add pwire `\\x' because a signal with the same name was already created" 1
read_verilog -pwires <<EOT
module top;
wire x;
assign x = 1;
localparam x = 2;
endmodule
EOT