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YosysHQ.yosys/tests/arch/xilinx
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Benjamin Barzen 8611429237 ABC9: Cell Port Bug Patch (#3670) 
* ABC9: RAMB36E1 Bug Patch

* Add simplified testcase

* Also fix xaiger writer for under-width output ports

* Remove old testcase

* Missing top-level input port

* Fix tabs

---------

Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2023-04-22 16:24:36 -07:00
..
.gitignore
Moved all tests in arch sub directory
2019-10-18 11:06:12 +02:00
abc9_dff.ys
Fix tests for check in equiv_opt
2022-10-07 16:04:51 +02:00
add_sub.ys
xilinx: Initial support for LUT4 devices.
2020-02-07 09:03:22 +01:00
adffs.ys
Make test without iopads
2019-12-28 16:22:24 +01:00
asym_ram_sdp_read_wider.v
Asymmetric port ram tests with Xilinx
2023-02-21 05:23:14 +13:00
asym_ram_sdp_write_wider.v
Asymmetric port ram tests with Xilinx
2023-02-21 05:23:14 +13:00
asym_ram_sdp.ys
Asymmetric port ram tests with Xilinx
2023-02-21 05:23:14 +13:00
attributes_test.ys
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
blockram.ys
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
bug1460.ys
Make test without iopads
2019-12-28 16:22:24 +01:00
bug1462.ys
xilinx_dsp: another typo; move xilinx specific test
2020-01-17 17:07:03 -08:00
bug1480.ys
Cleanup tests
2020-02-27 10:17:29 -08:00
bug1598.ys
Add #1598 testcase
2019-12-27 16:44:57 -08:00
bug1605.ys
Added a test case
2020-01-01 16:24:30 +01:00
bug3670.v
ABC9: Cell Port Bug Patch (#3670)
2023-04-22 16:24:36 -07:00
bug3670.ys
ABC9: Cell Port Bug Patch (#3670)
2023-04-22 16:24:36 -07:00
counter.ys
Fix tests
2020-01-10 14:48:01 +01:00
dffs.ys
abc9_ops: -reintegrate to use derived_type for box_ports
2020-02-05 14:46:48 -08:00
dsp_abc9.ys
xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)
2020-09-23 09:15:24 -07:00
dsp_cascade.ys
Fix new tests
2019-12-28 16:43:19 +01:00
dsp_fastfir.ys
Make test without iopads
2019-12-28 16:22:24 +01:00
dsp_simd.ys
Moved all tests in arch sub directory
2019-10-18 11:06:12 +02:00
fsm.ys
FfData: some refactoring.
2021-10-07 04:24:06 +02:00
latches.ys
opt_expr: Remove -clkinv option, make it the default.
2020-07-31 00:08:15 +02:00
logic.ys
Make test without iopads
2019-12-28 16:22:24 +01:00
lutram.ys
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
macc_tb.v
Moved all tests in arch sub directory
2019-10-18 11:06:12 +02:00
macc.sh
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
macc.v
tests: xilinx macc test to have initval, shorten BMC depth for runtime
2020-05-25 10:09:05 -07:00
macc.ys
tests: xilinx macc test to have initval, shorten BMC depth for runtime
2020-05-25 10:09:05 -07:00
mul_unsigned.v
Moved all tests in arch sub directory
2019-10-18 11:06:12 +02:00
mul_unsigned.ys
Fix new tests
2019-12-28 16:43:19 +01:00
mul.ys
Fix new tests
2019-12-28 16:43:19 +01:00
mux_lut4.ys
xilinx: Initial support for LUT4 devices.
2020-02-07 09:03:22 +01:00
mux.ys
xilinx_dffopt: Don't crash on missing IS_*_INVERTED.
2021-01-27 00:32:00 +01:00
nosrl.ys
xilinx: Fix srl regression.
2020-07-12 23:41:27 +02:00
opt_lut_ins.ys
Fix tests for check in equiv_opt
2022-10-07 16:04:51 +02:00
pmgen_xilinx_srl.ys
satgen: Add support for dffe, sdff, sdffe, sdffce cells.
2020-07-24 03:19:21 +02:00
priority_memory.v
Tests for ram_style = "huge"
2023-02-21 05:23:15 +13:00
priority_memory.ys
Tests for ram_style = "huge"
2023-02-21 05:23:15 +13:00
run-test.sh
tests: Centralize test collection and Makefile generation
2020-09-21 15:07:02 +02:00
shifter.ys
Make test without iopads
2019-12-28 16:22:24 +01:00
tribuf.sh
Fix the tests we just broke
2021-12-10 00:22:37 +01:00
tribuf.ys
Addressed review comments
2019-12-21 20:23:23 +01:00
xilinx_dffopt_blacklist.txt
xilinx: Add xilinx_dffopt pass (#1557)
2019-12-18 13:43:43 +01:00
xilinx_dffopt.ys
Fix tests for check in equiv_opt
2022-10-07 16:04:51 +02:00
xilinx_dsp.ys
tests: read +/xilinx/cell_sim.v before xilinx_dsp test
2020-04-22 17:50:30 -07:00
xilinx_srl.v
tests: fix some test warnings
2020-05-25 10:07:58 -07:00
xilinx_srl.ys
Moved all tests in arch sub directory
2019-10-18 11:06:12 +02:00