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fd2fb4f0f0132499ec4db3ce4d85f57c5ab618f8
YosysHQ.yosys
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tests
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svinterfaces
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svinterface1.sv
Ruben Undheim
d5aac2650f
Basic test for checking correct synthesis of SystemVerilog interfaces
2018-10-18 22:40:53 +02:00
2.5 KiB
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