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cleaned up fe6

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aap
2019-10-26 17:33:39 +02:00
parent 9dfa20df82
commit 5720149b68
3 changed files with 0 additions and 273 deletions
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160
fe6/hps_0.h
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#ifndef _ALTERA_HPS_0_H_
#define _ALTERA_HPS_0_H_
/*
* This file was automatically generated by the swinfo2header utility.
*
* Created from SOPC Builder system 'soc_system' in
* file '/cygdrive/e/DE0_Nano_SoC/Dev/HPS_CONTROL_FPGA_LED/soc_system.sopcinfo'.
*/
/*
* This file contains macros for module 'hps_0' and devices
* connected to the following masters:
* h2f_axi_master
* h2f_lw_axi_master
*
* Do not include this header file and another header file created for a
* different module or master group at the same time.
* Doing so may result in duplicate macro names.
* Instead, use the system header file which has macros with unique names.
*/
/*
* Macros for device 'onchip_memory2_0', class 'altera_avalon_onchip_memory2'
* The macros are prefixed with 'ONCHIP_MEMORY2_0_'.
* The prefix is the slave descriptor.
*/
#define ONCHIP_MEMORY2_0_COMPONENT_TYPE altera_avalon_onchip_memory2
#define ONCHIP_MEMORY2_0_COMPONENT_NAME onchip_memory2_0
#define ONCHIP_MEMORY2_0_BASE 0x0
#define ONCHIP_MEMORY2_0_SPAN 65536
#define ONCHIP_MEMORY2_0_END 0xffff
#define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ONCHIP_MEMORY2_0_CONTENTS_INFO ""
#define ONCHIP_MEMORY2_0_DUAL_PORT 0
#define ONCHIP_MEMORY2_0_GUI_RAM_BLOCK_TYPE AUTO
#define ONCHIP_MEMORY2_0_INIT_CONTENTS_FILE soc_system_onchip_memory2_0
#define ONCHIP_MEMORY2_0_INIT_MEM_CONTENT 1
#define ONCHIP_MEMORY2_0_INSTANCE_ID NONE
#define ONCHIP_MEMORY2_0_NON_DEFAULT_INIT_FILE_ENABLED 0
#define ONCHIP_MEMORY2_0_RAM_BLOCK_TYPE AUTO
#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE DONT_CARE
#define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0
#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1
#define ONCHIP_MEMORY2_0_SIZE_VALUE 65536
#define ONCHIP_MEMORY2_0_WRITABLE 1
#define ONCHIP_MEMORY2_0_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
#define ONCHIP_MEMORY2_0_MEMORY_INFO_GENERATE_DAT_SYM 1
#define ONCHIP_MEMORY2_0_MEMORY_INFO_GENERATE_HEX 1
#define ONCHIP_MEMORY2_0_MEMORY_INFO_HAS_BYTE_LANE 0
#define ONCHIP_MEMORY2_0_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR
#define ONCHIP_MEMORY2_0_MEMORY_INFO_MEM_INIT_DATA_WIDTH 64
#define ONCHIP_MEMORY2_0_MEMORY_INFO_MEM_INIT_FILENAME soc_system_onchip_memory2_0
/*
* Macros for device 'sysid_qsys', class 'altera_avalon_sysid_qsys'
* The macros are prefixed with 'SYSID_QSYS_'.
* The prefix is the slave descriptor.
*/
#define SYSID_QSYS_COMPONENT_TYPE altera_avalon_sysid_qsys
#define SYSID_QSYS_COMPONENT_NAME sysid_qsys
#define SYSID_QSYS_BASE 0x10000
#define SYSID_QSYS_SPAN 8
#define SYSID_QSYS_END 0x10007
#define SYSID_QSYS_ID 2899645186
#define SYSID_QSYS_TIMESTAMP 1420572267
/*
* Macros for device 'led_pio', class 'altera_avalon_pio'
* The macros are prefixed with 'LED_PIO_'.
* The prefix is the slave descriptor.
*/
#define LED_PIO_COMPONENT_TYPE altera_avalon_pio
#define LED_PIO_COMPONENT_NAME led_pio
#define LED_PIO_BASE 0x10040
#define LED_PIO_SPAN 32
#define LED_PIO_END 0x1005f
#define LED_PIO_BIT_CLEARING_EDGE_REGISTER 0
#define LED_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define LED_PIO_CAPTURE 0
#define LED_PIO_DATA_WIDTH 4
#define LED_PIO_DO_TEST_BENCH_WIRING 0
#define LED_PIO_DRIVEN_SIM_VALUE 0
#define LED_PIO_EDGE_TYPE NONE
#define LED_PIO_FREQ 50000000
#define LED_PIO_HAS_IN 0
#define LED_PIO_HAS_OUT 1
#define LED_PIO_HAS_TRI 0
#define LED_PIO_IRQ_TYPE NONE
#define LED_PIO_RESET_VALUE 0
/*
* Macros for device 'dipsw_pio', class 'altera_avalon_pio'
* The macros are prefixed with 'DIPSW_PIO_'.
* The prefix is the slave descriptor.
*/
#define DIPSW_PIO_COMPONENT_TYPE altera_avalon_pio
#define DIPSW_PIO_COMPONENT_NAME dipsw_pio
#define DIPSW_PIO_BASE 0x10080
#define DIPSW_PIO_SPAN 32
#define DIPSW_PIO_END 0x1009f
#define DIPSW_PIO_IRQ 0
#define DIPSW_PIO_BIT_CLEARING_EDGE_REGISTER 1
#define DIPSW_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define DIPSW_PIO_CAPTURE 1
#define DIPSW_PIO_DATA_WIDTH 4
#define DIPSW_PIO_DO_TEST_BENCH_WIRING 0
#define DIPSW_PIO_DRIVEN_SIM_VALUE 0
#define DIPSW_PIO_EDGE_TYPE ANY
#define DIPSW_PIO_FREQ 50000000
#define DIPSW_PIO_HAS_IN 1
#define DIPSW_PIO_HAS_OUT 0
#define DIPSW_PIO_HAS_TRI 0
#define DIPSW_PIO_IRQ_TYPE EDGE
#define DIPSW_PIO_RESET_VALUE 0
/*
* Macros for device 'button_pio', class 'altera_avalon_pio'
* The macros are prefixed with 'BUTTON_PIO_'.
* The prefix is the slave descriptor.
*/
#define BUTTON_PIO_COMPONENT_TYPE altera_avalon_pio
#define BUTTON_PIO_COMPONENT_NAME button_pio
#define BUTTON_PIO_BASE 0x100c0
#define BUTTON_PIO_SPAN 32
#define BUTTON_PIO_END 0x100df
#define BUTTON_PIO_IRQ 1
#define BUTTON_PIO_BIT_CLEARING_EDGE_REGISTER 1
#define BUTTON_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define BUTTON_PIO_CAPTURE 1
#define BUTTON_PIO_DATA_WIDTH 4
#define BUTTON_PIO_DO_TEST_BENCH_WIRING 0
#define BUTTON_PIO_DRIVEN_SIM_VALUE 0
#define BUTTON_PIO_EDGE_TYPE FALLING
#define BUTTON_PIO_FREQ 50000000
#define BUTTON_PIO_HAS_IN 1
#define BUTTON_PIO_HAS_OUT 0
#define BUTTON_PIO_HAS_TRI 0
#define BUTTON_PIO_IRQ_TYPE EDGE
#define BUTTON_PIO_RESET_VALUE 0
/*
* Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart'
* The macros are prefixed with 'JTAG_UART_'.
* The prefix is the slave descriptor.
*/
#define JTAG_UART_COMPONENT_TYPE altera_avalon_jtag_uart
#define JTAG_UART_COMPONENT_NAME jtag_uart
#define JTAG_UART_BASE 0x20000
#define JTAG_UART_SPAN 16
#define JTAG_UART_END 0x2000f
#define JTAG_UART_IRQ 2
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8
#endif /* _ALTERA_HPS_0_H_ */

103
fe6/main_0.c
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#include "test.h"
#include <unistd.h>
#include <fcntl.h>
#include <sys/mman.h>
#include "hps_0.h"
#include "led.h"
#define H2F_BASE (0xC0000000)
#define PERIPH_BASE (0xFC000000)
#define PERIPH_SPAN (0x04000000)
#define PERIPH_MASK (PERIPH_SPAN - 1)
#define LWH2F_BASE (0xFF200000)
u64 *h2f_base;
u32 *virtual_base;
u32 *getLWH2Faddr(u32 offset)
{
return (u32*)((u32)virtual_base - PERIPH_BASE + (LWH2F_BASE+offset));
}
u64 *getH2Faddr(u32 offset)
{
return (u64*)((u32)h2f_base + offset);
}
volatile u64 *h2f_axi_onchipmem;
volatile u32 *h2f_lw_led_addr;
volatile u32 *h2f_lw_sw_addr;
int
main(int argc, char **argv)
{
int fd;
int i;
if((fd = open("/dev/mem", (O_RDWR | O_SYNC))) == -1) {
fprintf(stderr, "ERROR: could not open /dev/mem...\n");
return 1;
}
virtual_base = (u32*)mmap(nil, PERIPH_SPAN, (PROT_READ | PROT_WRITE), MAP_SHARED, fd, PERIPH_BASE);
if(virtual_base == MAP_FAILED) {
fprintf(stderr, "ERROR: mmap() failed...\n");
close(fd);
return 1;
}
h2f_base = (u64*)mmap(nil, 0x100000, (PROT_READ | PROT_WRITE), MAP_SHARED, fd, H2F_BASE);
if(h2f_base == MAP_FAILED) {
fprintf(stderr, "ERROR: mmap() failed...\n");
close(fd);
return 1;
}
h2f_lw_led_addr = getLWH2Faddr(LED_PIO_BASE);
h2f_lw_sw_addr = getLWH2Faddr(DIPSW_PIO_BASE);
h2f_axi_onchipmem = getH2Faddr(0);
volatile u32 *cntr_addr = getLWH2Faddr(0x10100);
printf("%d\n", *cntr_addr);
int n = 0;
// for(i = 0; i < 50000000; i++)
// for(i = 0; i < 1000000; i++)
// n = *cntr_addr;
// printf("%d\n", n);
// return 0;
h2f_axi_onchipmem[0] = 0xFFFF12345678;
h2f_axi_onchipmem[1] = 0xEEEE11111111;
h2f_axi_onchipmem[2] = 0xDDDD22222222;
h2f_axi_onchipmem[3] = 0xCCCC33333333;
h2f_axi_onchipmem[4] = 0xBBBB44444444;
for(i = 0; i < 5; i++)
printf("%llX\n", h2f_axi_onchipmem[i]);
while(1) {
printf("LED ON\n");
for(i=0; i<=8; i++) {
LEDR_LightCount(i);
usleep(100*1000);
}
printf("LED OFF\n");
for(i=0; i<=8; i++) {
LEDR_OffCount(i);
usleep(100*1000);
}
printf("sw: %X\n", *h2f_lw_sw_addr);
}
if(munmap(virtual_base, PERIPH_SPAN) != 0) {
fprintf(stderr, "ERROR: munmap() failed...\n");
close(fd);
return 1;
}
close(fd);
return 0;
}

10
fe6/test.h
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#include <stdio.h>
#include <stdint.h>
#define nil NULL
typedef uint64_t u64;
typedef uint32_t u32;
typedef uint8_t u8;
volatile u32 *h2f_lw_led_addr;