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fixed bug in fastmem

This commit is contained in:
aap 2016-10-28 19:12:47 +02:00
parent ff8882ab38
commit 91f93179bb
3 changed files with 5 additions and 7 deletions

View File

@ -2479,13 +2479,12 @@ pulse(et0){
}
pulse(et0a){
static int gen = 0;
trace("ET0A\n");
debug("%o: ", apr->pc);
if((apr->inst & 0700) != 0700)
debug("%d %s\n", gen++, names[apr->inst]);
debug("%s\n", names[apr->inst]);
else
debug("%d %s\n", gen++, ionames[apr->io_inst>>5 & 7]);
debug("%s\n", ionames[apr->io_inst>>5 & 7]);
if(PI_HOLD)
set_pih(apr, apr->pi_req); // 8-3, 8-4

View File

@ -661,7 +661,6 @@ main(int argc, char *argv[])
extra_l = e; e += 1;
initapr(&apr);
// initmem();
coremems[0] = makecoremem("mem_0");
coremems[1] = makecoremem("mem_1");
coremems[2] = makecoremem("mem_2");

View File

@ -144,14 +144,14 @@ wakeff(Mem *mem, Membus *bus)
if(bus != mem->bus[ff->fmc_p_sel])
return 1;
fma = bus->c12>>4 & 017;
fma_rd_rq = !!(bus->c12 & MEMBUS_RD_RQ);
fma_wr_rq = !!(bus->c12 & MEMBUS_WR_RQ);
if(!ff->fmc_act && bus->c12 & MEMBUS_RQ_CYC){
//trace(" accepting memory cycle from proc %d\n", ff->fmc_p_sel);
ff->fmc_act = 1;
fma = bus->c12>>4 & 017;
//trace(" sending ADDR ACK\n");
//trace(" sending ADDR ACK %o\n", fma);
bus->c12 |= MEMBUS_MAI_ADDR_ACK;
if(fma_rd_rq){
@ -168,7 +168,7 @@ wakeff(Mem *mem, Membus *bus)
}
fmc_wr_sel = ff->fmc_act && !fma_rd_rq;
if(fmc_wr_sel && ff->fmc_wr && bus->c34){
//trace(" writing\n");
//trace(" writing fmem %o %012lo\n", fma, bus->c34);
ff->ff[fma] |= bus->c34 & FW;
bus->c34 = 0;
}