mirror of
https://github.com/aap/pdp6.git
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KA compatibility
This commit is contained in:
aap
parent
77c02726f5
commit
9d08e7306e
@ -1,4 +1,4 @@
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#include "fe6.h"
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#include "../fe.h"
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#include <unistd.h>
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/* Memory mapped PDP-6 interface */
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55
fe6/6/flags.inc
Normal file
55
fe6/6/flags.inc
Normal file
@ -0,0 +1,55 @@
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const char *ff0str =
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"%c KEY %c KEY %c KEY %c KEY DEP %c KEY %c MC %c MC %c MC\r\n"
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" EX ST EX SYNC DEP ST SYNC RD/WR RD WR RQ\r\n";
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const char *ff1str =
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"%c IF1A %c AF0 %c AF3 %c AF3A %c KEY %c F1A %c F4A %c F6A\r\n"
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" AR PSE\r\n";
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const char *ff2str =
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"%c SF3 %c SF5A %c SF7 %c AR %c BLT %c BLT %c BLT %c IOT\r\n"
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" COM F0A F3A F5A F0A\r\n";
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const char *ff3str =
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"%c FPF1 %c FPF2 %c FAF1 %c FAF2 %c FAF3 %c FAF4 %c FMF1 %c FMF2\r\n"
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"\r\n";
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const char *ff4str =
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"%c FDF1 %c FDF2 %c NR RND %c NRF1 %c NRF2 %c NRF3 %c FSF1 %c CHF7\r\n"
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"\r\n";
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const char *ff5str =
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"%c DSF1 %c DSF2 %c DSF3 %c DSF4 %c DSF5 %c DSF6 %c DSF7 %c DSF8\r\n"
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"\r\n";
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const char *ff6str =
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"%c DSF9 %c MSF1 %c MPF1 %c MPF2 %c SPLIT %c STOP %c SHF1 %c SC=777\r\n"
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" SYNC SYNC\r\n";
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const char *ff7str =
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"%c CHF1 %c CHF2 %c CHF3 %c CHF4 %c CHF5 %c CHF6 %c LCF1 %c DCF1\r\n"
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"\r\n";
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const char *ff8str =
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"%c PI OV %c PI CYC %c PI REQ %c IOT GO %c A LONG %c MA=MAS %c UUO F1 %c PDL OV\r\n"
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"\r\n";
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const char *ff9str =
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"%c FE1 %c FE2 %c FE3 %c FE4 %c FE5 %c FE6 %c FE7 %c FE8\r\n"
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"\r\n";
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const char *ff10str =
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"%c SC1 %c SC2 %c SC3 %c SC4 %c SC5 %c SC6 %c SC7 %c SC8\r\n"
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"\r\n";
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const char *ff11str =
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"%c EXEC %c CPA %c EX %c EX UUO %c EX PI %c MQ36 %c SC0 %c FE0\r\n"
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" MODE ILL OP ILL OP SYNC SYNC\r\n";
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const char *ff12str =
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"%c RIM %c CRY0 v %c AR CRY %c AR CRY %c AR OV %c AR CRY %c AR CRY %c PC CHG\r\n"
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" SBR CRY1 0 1 FLG 0 FLG 1 FLG FLG\r\n";
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const char *ff13str =
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"%c NONEX %c CLOCK %c CLOCK %c PC CHG %c AR OV %c PIA 33 %c PIA 34 %c PIA 35\r\n"
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" MEM EN FLG EN EN\r\n";
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@ -1,8 +1,7 @@
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#include "fe6.h"
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#include "../fe.h"
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#include <unistd.h>
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#include <fcntl.h>
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#include <sys/mman.h>
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//#include "hps_0.h"
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#define H2F_BASE (0xC0000000)
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@ -378,13 +377,7 @@ static void waitmemstop(void)
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int i;
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if(!isrunning())
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return;
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for(i = 0; i < 10; i++){
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if(isstopped())
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return;
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usleep(100);
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}
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keytoggle(MM6_MEMSTOP);
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for(i = 0; i < 10; i++){
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for(i = 0; i < 20; i++){
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if(isstopped())
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return;
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usleep(100);
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@ -431,7 +424,6 @@ X typestr("<SETPC>\r\n");
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cpu_stopinst();
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X run = 0;
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// TODO: maybe INSTSTOP?
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keydown(MM6_MEMSTOP);
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keyup(MM6_ADRSTOP);
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set_ta(a);
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@ -443,6 +435,11 @@ X typestr("<SETPC>\r\n");
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keyup(MM6_MEMSTOP);
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keytoggle(MM6_INSTSTOP);
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X run = 0;
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h2f_apr[REG6_CTL2_DN] = MM6_THISEX;
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usleep(1000);
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h2f_apr[REG6_CTL2_UP] = MM6_THISEX;
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usleep(1000);
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X memstop = 0;
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}
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void
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@ -452,6 +449,7 @@ X typestr("<STOPINST>\r\n");
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if(!isrunning())
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return;
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// TODO: what if memory stop?
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keytoggle(MM6_INSTSTOP);
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waithalt();
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X run = 0;
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@ -464,9 +462,10 @@ X typestr("<STOPMEM>\r\n");
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if(!isrunning() || isstopped())
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return;
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keytoggle(MM6_MEMSTOP);
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keydown(MM6_MEMSTOP);
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waitmemstop();
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X memstop = 1;
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keyup(MM6_MEMSTOP);
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}
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static void
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@ -485,22 +484,12 @@ togglecont(void)
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void
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cpu_cont(void)
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{
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int stop;
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X typestr("<CONT>\r\n");
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if(isrunning())
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return;
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stop = isstopped();
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keyup(MM6_STOP);
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togglecont();
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// on stop the machine should halt after one instruction
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// so restart
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// BUG: if next instruction is HALT we'll continue past it
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if(stop){
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waithalt();
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togglecont();
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}
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}
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void
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@ -551,6 +540,7 @@ X typestr("<RESET>\r\n");
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if(isrunning())
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err("?R? ");
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keytoggle(MM6_RESET);
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typestr("\r\n");
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}
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#include "flags.inc"
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32
fe6/6/regs.h
Normal file
32
fe6/6/regs.h
Normal file
@ -0,0 +1,32 @@
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#define PDP_REGS \
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X("DS", APR_DS)\
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X("MAS", APR_MAS)\
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X("RPT", APR_RPT)\
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X("IR", APR_IR)\
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X("MI", APR_MI)\
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X("PC", APR_PC)\
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X("MA", APR_MA)\
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X("PIH", APR_PIH)\
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X("PIR", APR_PIR)\
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X("PIO", APR_PIO)\
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X("RUN", APR_RUN)\
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X("PION", APR_PION)\
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X("STOP", APR_STOP)
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#ifdef TEST
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#define PDP_REGS_TEST \
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X("CTL1", APR_CTL1_DN)\
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X("CTL1U", APR_CTL1_UP)\
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X("CTL2", APR_CTL2_DN)\
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X("CTL2U", APR_CTL2_UP)\
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X("MB", APR_MB)\
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X("AR", APR_AR)\
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X("MQ", APR_MQ)\
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X("TTY.TTI", TTY_TTI)\
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X("TTY.ST", TTY_ST)\
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X("PTR.PTR", PTR_PTR)\
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X("PTR.ST", PTR_ST)\
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X("PTR.FE", PTR_FE)\
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X("FE.REQ", FE_REQ)
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#else
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#define PDP_REGS_TEST
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#endif
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22
fe6/Makefile
22
fe6/Makefile
@ -1,13 +1,21 @@
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XX=/u/aap/de0-nano-soc/gcc-linaro-6.5.0-2018.12-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-
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CFLAGS=-DTEST
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all: fe6_emu fe6_fake fe6
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SRC=fe.c cmd.c util.c pdp6common.c
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fe6_emu: fe6.c emu6.c cmd.c util.c pdp6common.c
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$(CC) $(CFLAGS) -o $@ $^
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all: fe6_emu fe6_fake fe6 feka
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clean:
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rm fe6_emu fe6_fake fe6
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fe6_fake: fe6.c fake.c cmd.c util.c pdp6common.c
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$(CC) $(CFLAGS) -o $@ $^
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fe6: $(SRC) 6/real6.c
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$(XX)gcc -I6 $(CFLAGS) -o $@ $^
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fe6: fe6.c real6.c cmd.c util.c pdp6common.c
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$(XX)gcc $(CFLAGS) -o $@ $^
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fe6_fake: $(SRC) fake.c
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$(CC) -I6 $(CFLAGS) -o $@ $^
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fe6_emu: $(SRC) 6/emu6.c
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$(CC) -I6 $(CFLAGS) -o $@ $^
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feka: $(SRC) ka/real.c
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$(XX)gcc -Ika $(CFLAGS) -o $@ $^
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43
fe6/cmd.c
43
fe6/cmd.c
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#include "fe6.h"
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#include "fe.h"
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#include <unistd.h>
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#include <fcntl.h>
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@ -60,6 +60,33 @@ splitops(void)
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}
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}
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void
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loadsav(FILE *fp)
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{
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word iowd;
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word w;
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while(w = readwbak(fp), w != ~0){
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if(w >> 27 == 0254){
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printf("PC: %o\r\n", right(w));
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fflush(stdout);
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cpu_setpc(right(w));
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started = 1;
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return;
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}
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iowd = w;
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while(left(iowd) != 0){
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iowd += 01000001;
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w = readwbak(fp);
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if(w == ~0)
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goto format;
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deposit(right(iowd), w);
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}
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}
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format:
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printf("\r\nSAV format botch\r\n");
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fflush(stdout);
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}
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void
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loadsblk(FILE *fp)
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{
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@ -209,6 +236,19 @@ c_load(int argc, char *argv[])
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fclose(f);
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}
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void
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c_loadsav(int argc, char *argv[])
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{
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FILE *f;
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if(argc < 2)
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return;
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f = fopen(ops[1], "rb");
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if(f == nil)
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err("?F? ");
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loadsav(f);
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fclose(f);
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}
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struct dev devtab[] = {
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{ "ptr", O_RDONLY, -1, nil },
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{ "ptp", O_WRONLY | O_CREAT | O_TRUNC, -1, nil },
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@ -285,6 +325,7 @@ struct {
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void (*f)(int, char **);
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} cmdtab[] = {
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{ "load", c_load },
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{ "loadsav", c_loadsav },
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{ "dump", c_dump },
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{ "mount", c_mount },
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{ "unmount", c_unmount },
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@ -1,4 +1,4 @@
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#include "fe6.h"
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#include "fe.h"
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#include <unistd.h>
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static word memory[01000000];
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@ -3,7 +3,7 @@
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#include <unistd.h>
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#include <setjmp.h>
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#include "fe6.h"
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#include "fe.h"
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struct termios tiosaved;
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char erasec, killc, intrc;
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@ -224,20 +224,6 @@ struct Symbol
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Symbol symtab[] = {
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{ "SM", 01000000 },
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// { "MM", 02000000 },
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{ "DS", APR_DS },
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{ "MAS", APR_MAS },
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{ "RPT", APR_RPT },
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{ "IR", APR_IR },
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{ "MI", APR_MI },
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{ "PC", APR_PC },
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{ "MA", APR_MA },
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{ "PIH", APR_PIH },
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{ "PIR", APR_PIR },
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{ "PIO", APR_PIO },
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{ "RUN", APR_RUN },
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{ "PION", APR_PION },
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{ "STOP", APR_STOP },
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{ "LED", 01001000 },
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{ "SW", 01001001 },
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@ -254,21 +240,12 @@ Symbol symtab[] = {
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{ "%DC", 0200 },
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{ "%UTC", 0204 },
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{ "%UTS", 0210 },
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#ifdef TEST
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{ "CTL1U", APR_CTL1_UP },
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{ "CTL1", APR_CTL1_DN },
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{ "CTL2U", APR_CTL2_UP },
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{ "CTL2", APR_CTL2_DN },
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{ "MB", APR_MB },
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{ "AR", APR_AR },
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{ "MQ", APR_MQ },
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{ "TTY.TTI", TTY_TTI },
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{ "TTY.ST", TTY_ST },
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{ "PTR.PTR", PTR_PTR },
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{ "PTR.ST", PTR_ST },
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{ "PTR.FE", PTR_FE },
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{ "FE.REQ", FE_REQ },
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#endif
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#define X(str, name) { str, name },
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PDP_REGS
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PDP_REGS_TEST
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#undef X
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{ nil, 0 },
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};
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@ -554,6 +531,15 @@ runline(void)
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}
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}
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void
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zerocore(void)
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{
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hword a;
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for(a = 0; a < MAXMEM; a++)
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deposit(a, 0);
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typestr("\r\n");
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}
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void
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quit(void)
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{
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@ -755,6 +741,13 @@ main()
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combine(q);
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break;
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case 'Z':
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if(flags & CCF)
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zerocore();
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else
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err(" ?? ");
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break;
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case ALT:
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if(flags & CF)
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flags |= CCF;
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@ -20,38 +20,14 @@ typedef uint8_t u8;
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#define MAXMEM (16*1024)
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#include "regs.h"
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enum {
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APR_DS = 01000020,
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APR_MAS,
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APR_RPT,
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APR_IR,
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APR_MI,
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APR_PC,
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APR_MA,
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APR_PIH,
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APR_PIR,
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APR_PIO,
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APR_RUN,
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APR_PION,
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APR_STOP,
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#ifdef TEST
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APR_CTL1_DN,
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APR_CTL1_UP,
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APR_CTL2_DN,
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APR_CTL2_UP,
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APR_MB,
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APR_AR,
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APR_MQ,
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TTY_TTI,
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TTY_ST,
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PTR_PTR,
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PTR_ST,
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PTR_FE,
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FE_REQ,
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#endif
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FAKEFAKE = 01000017,
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#define X(str, name) name,
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PDP_REGS
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PDP_REGS_TEST
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#undef X
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APR_END,
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};
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713
fe6/ka/real.c
Executable file
713
fe6/ka/real.c
Executable file
@ -0,0 +1,713 @@
|
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#include "../fe.h"
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#include <unistd.h>
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#include <fcntl.h>
|
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#include <sys/mman.h>
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|
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#define H2F_BASE (0xC0000000)
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|
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#define PERIPH_BASE (0xFC000000)
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#define PERIPH_SPAN (0x04000000)
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#define PERIPH_MASK (PERIPH_SPAN - 1)
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#define LWH2F_BASE (0xFF200000)
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|
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/* Memory mapped KA10 interface */
|
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enum
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{
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/* keys, switches and some lights */
|
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REG_SW_DN = 0,
|
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REG_SW_UP = 1,
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// keys
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MMKA_DEP_NXT = 1,
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MMKA_DEP = 2,
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MMKA_EX_NXT = 4,
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MMKA_EX = 010,
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MMKA_XCT = 020,
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MMKA_RESET = 040,
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MMKA_STOP = 0100,
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MMKA_CONT = 0200,
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MMKA_START = 0400,
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MMKA_READIN = 01000,
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// switches
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MMKA_ADR_BRK = 02000,
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MMKA_ADR_STOP = 04000,
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MMKA_ADR_WR = 010000,
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MMKA_ADR_RD = 020000,
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MMKA_ADR_INST = 040000,
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MMKA_RPT = 0100000,
|
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MMKA_NXM_STOP = 0200000,
|
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MMKA_PAR_STOP = 0400000,
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MMKA_SING_CYC = 01000000,
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MMKA_SING_INST = 02000000,
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/* lights */
|
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MMKA_MEM_STOP = 04000000,
|
||||
MMKA_USER = 010000000,
|
||||
MMKA_PROG_STOP = 020000000,
|
||||
MMKA_PWR_ON = 040000000,
|
||||
MMKA_RUN = 0100000000,
|
||||
|
||||
/* Maintenance switches */
|
||||
REG_MAINT_DN = 2,
|
||||
REG_MAINT_UP = 3,
|
||||
MMKA_RDI_SEL = 0177,
|
||||
MMKA_MI_PROG_DIS = 0200,
|
||||
MMKA_RPT_BYPASS = 0400,
|
||||
MMKA_FM_EN = 01000,
|
||||
MMKA_SC_STOP = 02000,
|
||||
|
||||
/* switches and knobs */
|
||||
REG_DSLT = 4,
|
||||
REG_DSRT = 5,
|
||||
REG_AS = 6,
|
||||
REG_REPEAT = 7,
|
||||
|
||||
/* lights */
|
||||
REG_IR = 010,
|
||||
REG_MILT = 011,
|
||||
REG_MIRT = 012,
|
||||
REG_PC = 013,
|
||||
REG_MA = 014,
|
||||
REG_PI = 015,
|
||||
|
||||
REG_ARLT = 016,
|
||||
REG_ARRT = 017,
|
||||
REG_BRLT = 020,
|
||||
REG_BRRT = 021,
|
||||
REG_MQLT = 022,
|
||||
REG_MQRT = 023,
|
||||
REG_ADLT = 024,
|
||||
REG_ADRT = 025,
|
||||
REG_SC_FE = 026,
|
||||
REG_SCAD = 027,
|
||||
REG_KEY_OPR = 030,
|
||||
REG_F_S_FMA = 031,
|
||||
REG_PR_RL = 032,
|
||||
REG_RLA_MEM = 033,
|
||||
REG_CPA_MISC = 034,
|
||||
REG_REST = 035,
|
||||
|
||||
REG_TTY = 040,
|
||||
REG_PTP = 041,
|
||||
REG_PTR = 042,
|
||||
REG_PTR_LT = 043,
|
||||
REG_PTR_RT = 044,
|
||||
};
|
||||
|
||||
enum {
|
||||
FEREG_REQ = 0,
|
||||
FEREG_PTR,
|
||||
FEREG_PTP
|
||||
};
|
||||
|
||||
|
||||
static u64 *h2f_base;
|
||||
static u32 *virtual_base;
|
||||
static u32 *getLWH2Faddr(u32 offset)
|
||||
{
|
||||
return (u32*)((u32)virtual_base - PERIPH_BASE + (LWH2F_BASE+offset));
|
||||
}
|
||||
static u64 *getH2Faddr(u32 offset)
|
||||
{
|
||||
return (u64*)((u32)h2f_base + offset);
|
||||
}
|
||||
|
||||
static int memfd;
|
||||
static volatile u32 *h2f_cmemif;
|
||||
static volatile u32 *h2f_fmemif;
|
||||
static volatile u32 *h2f_apr;
|
||||
static volatile u32 *h2f_fe;
|
||||
|
||||
void
|
||||
deposit(hword a, word w)
|
||||
{
|
||||
if(a < 020){
|
||||
h2f_fmemif[0] = a & 017;
|
||||
h2f_fmemif[1] = w & RT;
|
||||
h2f_fmemif[2] = (w >> 18) & RT;
|
||||
}else if(a < 01000020){
|
||||
h2f_cmemif[0] = a & RT;
|
||||
h2f_cmemif[1] = w & RT;
|
||||
h2f_cmemif[2] = (w >> 18) & RT;
|
||||
}else switch(a){
|
||||
case APR_DS:
|
||||
h2f_apr[REG_DSLT] = w>>18 & RT;
|
||||
h2f_apr[REG_DSRT] = w & RT;
|
||||
break;
|
||||
case APR_AS:
|
||||
h2f_apr[REG_AS] = w & RT;
|
||||
break;
|
||||
case APR_RPT:
|
||||
h2f_apr[REG_REPEAT] = w;
|
||||
break;
|
||||
|
||||
#ifdef TEST
|
||||
case APR_SW_DN:
|
||||
h2f_apr[REG_SW_DN] = w;
|
||||
break;
|
||||
case APR_SW_UP:
|
||||
h2f_apr[REG_SW_UP] = w;
|
||||
break;
|
||||
case APR_MAINT_DN:
|
||||
h2f_apr[REG_MAINT_DN] = w;
|
||||
break;
|
||||
case APR_MAINT_UP:
|
||||
h2f_apr[REG_MAINT_UP] = w;
|
||||
break;
|
||||
|
||||
case PTR_FE:
|
||||
h2f_fe[FEREG_PTR] = w;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
word
|
||||
examine(hword a)
|
||||
{
|
||||
u64 w;
|
||||
w = 0;
|
||||
|
||||
if(a < 020){
|
||||
h2f_fmemif[0] = a & 017;
|
||||
w = h2f_fmemif[2] & RT;
|
||||
w <<= 18;
|
||||
w |= h2f_fmemif[1] & RT;
|
||||
}else if(a < 01000020){
|
||||
h2f_cmemif[0] = a & RT;
|
||||
w = h2f_cmemif[2] & RT;
|
||||
w <<= 18;
|
||||
w |= h2f_cmemif[1] & RT;
|
||||
}else switch(a){
|
||||
case APR_DS:
|
||||
w = h2f_apr[REG_DSLT] & RT;
|
||||
w <<= 18;
|
||||
w |= h2f_apr[REG_DSRT] & RT;
|
||||
return w;
|
||||
case APR_AS:
|
||||
w = h2f_apr[REG_AS];
|
||||
break;
|
||||
case APR_RPT:
|
||||
w = h2f_apr[REG_REPEAT];
|
||||
break;
|
||||
|
||||
case APR_IR:
|
||||
return h2f_apr[REG_IR] & RT;
|
||||
case APR_MI:
|
||||
w = h2f_apr[REG_MILT] & RT;
|
||||
w <<= 18;
|
||||
w |= h2f_apr[REG_MIRT] & RT;
|
||||
return w;
|
||||
case APR_PC:
|
||||
return h2f_apr[REG_PC];
|
||||
case APR_MA:
|
||||
return h2f_apr[REG_MA];
|
||||
case APR_PIO:
|
||||
return h2f_apr[REG_PI]>>1 & 0177;
|
||||
case APR_PIR:
|
||||
return h2f_apr[REG_PI]>>8 & 0177;
|
||||
case APR_PIH:
|
||||
return h2f_apr[REG_PI]>>15 & 0177;
|
||||
case APR_PION:
|
||||
return h2f_apr[REG_PI] & 1;
|
||||
|
||||
case APR_RUN:
|
||||
return !!(h2f_apr[REG_SW_DN] & MMKA_RUN);
|
||||
case APR_STOP:
|
||||
return !!(h2f_apr[REG_SW_DN] & MMKA_MEM_STOP);
|
||||
|
||||
#ifdef TEST
|
||||
case APR_SW_DN:
|
||||
return h2f_apr[REG_SW_DN];
|
||||
case APR_SW_UP:
|
||||
return h2f_apr[REG_SW_UP];
|
||||
case APR_MAINT_DN:
|
||||
return h2f_apr[REG_MAINT_DN];
|
||||
case APR_MAINT_UP:
|
||||
return h2f_apr[REG_MAINT_UP];
|
||||
case APR_AR:
|
||||
w = h2f_apr[REG_ARLT] & RT;
|
||||
w <<= 18;
|
||||
w |= h2f_apr[REG_ARRT] & RT;
|
||||
return w;
|
||||
case APR_BR:
|
||||
w = h2f_apr[REG_BRLT] & RT;
|
||||
w <<= 18;
|
||||
w |= h2f_apr[REG_BRRT] & RT;
|
||||
return w;
|
||||
case APR_MQ:
|
||||
w = h2f_apr[REG_MQLT] & RT;
|
||||
w <<= 18;
|
||||
w |= h2f_apr[REG_MQRT] & RT;
|
||||
return w;
|
||||
case APR_AD:
|
||||
w = h2f_apr[REG_ADLT] & RT;
|
||||
w <<= 18;
|
||||
w |= h2f_apr[REG_ADRT] & RT;
|
||||
return w;
|
||||
|
||||
case TTY_TTI:
|
||||
return (h2f_apr[REG_TTY]>>9) & 0377;
|
||||
case TTY_ST:
|
||||
return h2f_apr[REG_TTY] & 0177;
|
||||
case PTR_PTR:
|
||||
w = h2f_apr[REG_PTR_LT];
|
||||
w <<= 18;
|
||||
w |= h2f_apr[REG_PTR_RT] & RT;
|
||||
return w;
|
||||
case PTR_ST:
|
||||
return h2f_apr[REG_PTR] & 0177;
|
||||
|
||||
case FE_REQ:
|
||||
return h2f_fe[FEREG_REQ];
|
||||
#endif
|
||||
}
|
||||
return w;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void set_ta(hword a)
|
||||
{
|
||||
h2f_apr[REG_AS] = a & RT;
|
||||
}
|
||||
|
||||
static void set_td(word d)
|
||||
{
|
||||
h2f_apr[REG_DSLT] = d>>18 & RT;
|
||||
h2f_apr[REG_DSRT] = d & RT;
|
||||
}
|
||||
|
||||
static void keydown(u32 k)
|
||||
{
|
||||
h2f_apr[REG_SW_DN] = k;
|
||||
// TODO: still needed with KA?
|
||||
if(k & MMKA_STOP)
|
||||
usleep(1000); // wait for AT INH to go down
|
||||
}
|
||||
|
||||
static void keyup(u32 k)
|
||||
{
|
||||
h2f_apr[REG_SW_UP] = k;
|
||||
}
|
||||
|
||||
static void keytoggle(u32 k) {
|
||||
keydown(k);
|
||||
usleep(1000); // TODO: maybe don't sleep? or different duration?
|
||||
keyup(k);
|
||||
}
|
||||
|
||||
int isrunning(void)
|
||||
{
|
||||
return !!(h2f_apr[REG_SW_DN] & MMKA_RUN);
|
||||
}
|
||||
int isstopped(void)
|
||||
{
|
||||
return !!(h2f_apr[REG_SW_DN] & MMKA_MEM_STOP);
|
||||
}
|
||||
|
||||
static void waithalt(void)
|
||||
{
|
||||
int i;
|
||||
for(i = 0; i < 10; i++){
|
||||
if(!isrunning())
|
||||
return;
|
||||
usleep(100);
|
||||
}
|
||||
keytoggle(MMKA_STOP);
|
||||
for(i = 0; i < 10; i++){
|
||||
if(!isrunning())
|
||||
return;
|
||||
usleep(100);
|
||||
}
|
||||
typestr("not halted!!!\r\n");
|
||||
}
|
||||
|
||||
static void waitmemstop(void)
|
||||
{
|
||||
int i;
|
||||
if(!isrunning())
|
||||
return;
|
||||
for(i = 0; i < 20; i++){
|
||||
if(isstopped())
|
||||
return;
|
||||
usleep(100);
|
||||
}
|
||||
typestr("not stopped!!!\r\n");
|
||||
}
|
||||
|
||||
static int run;
|
||||
static int memstop;
|
||||
#define X if(0)
|
||||
|
||||
void
|
||||
cpu_start(hword a)
|
||||
{
|
||||
X typestr("<GO>\r\n");
|
||||
|
||||
cpu_stopinst();
|
||||
X run = 0;
|
||||
keyup(MMKA_SING_INST | MMKA_ADR_STOP);
|
||||
set_ta(a);
|
||||
keytoggle(MMKA_START);
|
||||
X run = 1;
|
||||
X memstop = 0;
|
||||
}
|
||||
|
||||
void
|
||||
cpu_readin(hword a)
|
||||
{
|
||||
X typestr("<READIN>\r\n");
|
||||
|
||||
cpu_stopinst();
|
||||
X run = 0;
|
||||
keyup(MMKA_SING_INST | MMKA_ADR_STOP);
|
||||
h2f_apr[REG_MAINT_UP] = 0177;
|
||||
h2f_apr[REG_MAINT_DN] = a & 0177;
|
||||
keytoggle(MMKA_READIN);
|
||||
X run = 1;
|
||||
X memstop = 0;
|
||||
}
|
||||
|
||||
void
|
||||
cpu_setpc(hword a)
|
||||
{
|
||||
X typestr("<SETPC>\r\n");
|
||||
|
||||
cpu_stopinst();
|
||||
X run = 0;
|
||||
keydown(MMKA_SING_CYC);
|
||||
keyup(MMKA_ADR_STOP);
|
||||
set_ta(a);
|
||||
keytoggle(MMKA_START);
|
||||
X run = 1;
|
||||
X memstop = 0;
|
||||
waitmemstop();
|
||||
X memstop = 1;
|
||||
keyup(MMKA_SING_CYC);
|
||||
keytoggle(MMKA_STOP);
|
||||
X run = 0;
|
||||
keytoggle(MMKA_EX);
|
||||
usleep(1000);
|
||||
X memstop = 0;
|
||||
}
|
||||
|
||||
void
|
||||
cpu_stopinst(void)
|
||||
{
|
||||
X typestr("<STOPINST>\r\n");
|
||||
|
||||
if(!isrunning())
|
||||
return;
|
||||
// TODO: what if memory stop?
|
||||
keytoggle(MMKA_STOP);
|
||||
keydown(MMKA_SING_INST);
|
||||
waithalt();
|
||||
X run = 0;
|
||||
keyup(MMKA_SING_INST);
|
||||
}
|
||||
|
||||
void
|
||||
cpu_stopmem(void)
|
||||
{
|
||||
X typestr("<STOPMEM>\r\n");
|
||||
|
||||
if(!isrunning() || isstopped())
|
||||
return;
|
||||
keydown(MMKA_SING_CYC);
|
||||
waitmemstop();
|
||||
X memstop = 1;
|
||||
keyup(MMKA_SING_CYC);
|
||||
}
|
||||
|
||||
static void
|
||||
togglecont(void)
|
||||
{
|
||||
keytoggle(MMKA_CONT);
|
||||
}
|
||||
|
||||
void
|
||||
cpu_cont(void)
|
||||
{
|
||||
X typestr("<CONT>\r\n");
|
||||
|
||||
if(isrunning())
|
||||
return;
|
||||
keyup(MMKA_SING_CYC | MMKA_SING_INST | MMKA_ADR_STOP);
|
||||
togglecont();
|
||||
}
|
||||
|
||||
void
|
||||
cpu_nextinst(void)
|
||||
{
|
||||
X typestr("<NEXTINST>\r\n");
|
||||
|
||||
if(isrunning() && !isstopped())
|
||||
err("?R? ");
|
||||
keydown(MMKA_SING_INST);
|
||||
X run = 0;
|
||||
togglecont();
|
||||
waithalt();
|
||||
X run = 0;
|
||||
keyup(MMKA_SING_INST);
|
||||
}
|
||||
|
||||
void
|
||||
cpu_nextmem(void)
|
||||
{
|
||||
X typestr("<NEXTMEM>\r\n");
|
||||
|
||||
if(isrunning() && !isstopped())
|
||||
err("?R? ");
|
||||
keydown(MMKA_SING_CYC);
|
||||
togglecont();
|
||||
waitmemstop();
|
||||
X memstop = 1;
|
||||
keyup(MMKA_SING_CYC);
|
||||
}
|
||||
|
||||
void
|
||||
cpu_exec(word inst)
|
||||
{
|
||||
X typestr("<EXEC>\r\n");
|
||||
|
||||
if(isrunning())
|
||||
err("?R? ");
|
||||
set_td(inst);
|
||||
keytoggle(MMKA_XCT);
|
||||
}
|
||||
|
||||
void
|
||||
cpu_ioreset(void)
|
||||
{
|
||||
X typestr("<RESET>\r\n");
|
||||
|
||||
if(isrunning())
|
||||
err("?R? ");
|
||||
keytoggle(MMKA_RESET);
|
||||
typestr("\r\n");
|
||||
}
|
||||
|
||||
void
|
||||
cpu_printflags(void)
|
||||
{
|
||||
static const char *l = ".#";
|
||||
u32 ctl, pi;
|
||||
u32 sc_fe, scad, key_opr, f_s_fma, pr_rl, rla_mem, cpa_misc, rest;
|
||||
|
||||
ctl = h2f_apr[REG_SW_DN];
|
||||
pi = h2f_apr[REG_PI];
|
||||
sc_fe = h2f_apr[REG_SC_FE];
|
||||
scad = h2f_apr[REG_SCAD];
|
||||
key_opr = h2f_apr[REG_KEY_OPR];
|
||||
f_s_fma = h2f_apr[REG_F_S_FMA];
|
||||
pr_rl = h2f_apr[REG_PR_RL];
|
||||
rla_mem = h2f_apr[REG_RLA_MEM];
|
||||
cpa_misc = h2f_apr[REG_CPA_MISC];
|
||||
rest = h2f_apr[REG_REST];
|
||||
|
||||
printf("\r\n");
|
||||
printf("FE %03o SC %03o STOP %c\r\n", sc_fe&0777, sc_fe>>9&0777,
|
||||
l[!!(sc_fe & 01000000)]);
|
||||
printf("SCAD %03o\r\n", scad&0777);
|
||||
|
||||
printf("KEY F1 %c SYNC RQ %c SYNC %c RSET %c\r\n"
|
||||
" EXAM %c EX NXT %c DEP %c DEP NXT %c\r\n"
|
||||
" RDI %c STRT %c EXE %c CONT %c\r\n",
|
||||
l[!!(key_opr&040000000)],
|
||||
l[!!(key_opr&020000000)],
|
||||
l[!!(key_opr&010000000)],
|
||||
l[!!(key_opr&04000000)],
|
||||
l[!!(key_opr&02000000)],
|
||||
l[!!(key_opr&01000000)],
|
||||
l[!!(key_opr&0400000)],
|
||||
l[!!(key_opr&0200000)],
|
||||
l[!!(key_opr&0100000)],
|
||||
l[!!(key_opr&040000)],
|
||||
l[!!(key_opr&020000)],
|
||||
l[!!(key_opr&010000)]);
|
||||
|
||||
printf("OPR IF0 %c AF2 %c FF1 %c FF2 %c FF4 %c\r\n"
|
||||
" E UUOF %c E XCTF %c E LONG %c EF0 LONG %c\r\n"
|
||||
" SF1 %c SF6 %c SF8 %c\r\n",
|
||||
l[!!(key_opr&04000)],
|
||||
l[!!(key_opr&02000)],
|
||||
l[!!(key_opr&01000)],
|
||||
l[!!(key_opr&0400)],
|
||||
l[!!(key_opr&0200)],
|
||||
l[!!(key_opr&0100)],
|
||||
l[!!(key_opr&040)],
|
||||
l[!!(key_opr&020)],
|
||||
l[!!(key_opr&010)],
|
||||
l[!!(key_opr&04)],
|
||||
l[!!(key_opr&02)],
|
||||
l[!!(key_opr&01)]);
|
||||
|
||||
printf("FETCH FCE %c FCE PSE %c FAC INH %c FAC2 %c"
|
||||
" FCC ACLT %c FCC ACRT\r\n",
|
||||
l[!!(f_s_fma&040000)],
|
||||
l[!!(f_s_fma&020000)],
|
||||
l[!!(f_s_fma&010000)],
|
||||
l[!!(f_s_fma&04000)],
|
||||
l[!!(f_s_fma&02000)],
|
||||
l[!!(f_s_fma&01000)]);
|
||||
|
||||
printf("STORE SCE %c ST INH %c SAC2 %c SAC INH %c SAC=0 %c\r\n",
|
||||
l[!!(f_s_fma&0400)],
|
||||
l[!!(f_s_fma&0200)],
|
||||
l[!!(f_s_fma&0100)],
|
||||
l[!!(f_s_fma&040)],
|
||||
l[!!(f_s_fma&020)]);
|
||||
|
||||
printf("FMA %02o\r\n", f_s_fma & 017);
|
||||
|
||||
printf("PR RL %o\r\n", pr_rl);
|
||||
|
||||
printf("RLA %03o RLC %03o\r\n", rla_mem<<1 & 0776, rla_mem>>7 & 0776);
|
||||
printf("MEM MC RQ %c MC RD %c MC WR %c REQ CYC %c SPLIT SYNC %c\r\n"
|
||||
" FM EN %c FMA SEL %c FMA AC %c FMA AC2 %c FMA XR %c\r\n",
|
||||
l[!!(rla_mem&0200000000)],
|
||||
l[!!(rla_mem&0100000000)],
|
||||
l[!!(rla_mem&040000000)],
|
||||
l[!!(rla_mem&020000000)],
|
||||
l[!!(rla_mem&010000000)],
|
||||
l[!!(rla_mem&04000000)],
|
||||
l[!!(rla_mem&02000000)],
|
||||
l[!!(rla_mem&01000000)],
|
||||
l[!!(rla_mem&0400000)],
|
||||
l[!!(rla_mem&0200000)]);
|
||||
|
||||
printf("CPA PWR %c ADR BRK %c PAR ERR %c PAR EN %c PDL OV %c MEM PROT %c\r\n"
|
||||
" NXM FLAG %c CLK EN %c CLK FLAG %c FOV EN %c AROV EN %c\r\n"
|
||||
" PIA %o\r\n",
|
||||
l[!!(cpa_misc&020000)],
|
||||
l[!!(cpa_misc&010000)],
|
||||
l[!!(cpa_misc&04000)],
|
||||
l[!!(cpa_misc&02000)],
|
||||
l[!!(cpa_misc&01000)],
|
||||
l[!!(cpa_misc&0400)],
|
||||
l[!!(cpa_misc&0200)],
|
||||
l[!!(cpa_misc&0100)],
|
||||
l[!!(cpa_misc&040)],
|
||||
l[!!(cpa_misc&020)],
|
||||
l[!!(cpa_misc&010)],
|
||||
cpa_misc&07);
|
||||
|
||||
printf("MISC %o\r\n", cpa_misc>>14);
|
||||
|
||||
printf("EX ILL OP %c PI SYNC %c MODE SYNC %c IOT USER %c REL %c\r\n",
|
||||
l[!!(rest&020000)],
|
||||
l[!!(rest&010000)],
|
||||
l[!!(rest&04000)],
|
||||
l[!!(rest&02000)],
|
||||
l[!!(rest&01000)]);
|
||||
printf("PI OV %c CYC %c\r\n",
|
||||
l[!!(rest&0400)],
|
||||
l[!!(rest&0200)]);
|
||||
printf("BYTE LOAD %c DEP %c\r\n",
|
||||
l[!!(rest&0100)],
|
||||
l[!!(rest&040)]);
|
||||
printf("NR SHRT COND %c NOR %c RND %c\r\n",
|
||||
l[!!(rest&020)],
|
||||
l[!!(rest&010)],
|
||||
l[!!(rest&04)]);
|
||||
printf("AS= RLA %c FMA %c\r\n",
|
||||
l[!!(rest&02)],
|
||||
l[!!(rest&01)]);
|
||||
|
||||
printf("PIH/%03o PIR/%03o PIO/%03o PI ACTIVE/%o\r\n",
|
||||
pi>>15 & 0177, pi>>8 & 0177, pi>>1 & 0177, !!(pi & 1));
|
||||
printf("PWR %c RUN %c MCSTOP %c PROGSTOP %c USER %c\r\n",
|
||||
l[!!(ctl&MMKA_PWR_ON)],
|
||||
l[!!(ctl&MMKA_RUN)],
|
||||
l[!!(ctl&MMKA_MEM_STOP)],
|
||||
l[!!(ctl&MMKA_PROG_STOP)],
|
||||
l[!!(ctl&MMKA_USER)]);
|
||||
fflush(stdout);
|
||||
}
|
||||
|
||||
static void
|
||||
svc_ptr(void)
|
||||
{
|
||||
int fd;
|
||||
u8 c;
|
||||
|
||||
fd = devtab[DEV_PTR].fd;
|
||||
if(fd < 0)
|
||||
return;
|
||||
if(read(fd, &c, 1) == 1){
|
||||
printf("%d%d%d%d%d%d%d%d -> PTR\r\n",
|
||||
!!(c&0200), !!(c&0100), !!(c&040), !!(c&020), !!(c&010),
|
||||
!!(c&04), !!(c&02), !!(c&01));
|
||||
fflush(stdout);
|
||||
h2f_fe[FEREG_PTR] = c;
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
svc_ptp(void)
|
||||
{
|
||||
int fd;
|
||||
u8 c;
|
||||
|
||||
c = h2f_fe[FEREG_PTP];
|
||||
printf("PTP <- %d%d%d%d%d%d%d%d\r\n",
|
||||
!!(c&0200), !!(c&0100), !!(c&040), !!(c&020), !!(c&010),
|
||||
!!(c&04), !!(c&02), !!(c&01));
|
||||
fflush(stdout);
|
||||
|
||||
fd = devtab[DEV_PTP].fd;
|
||||
if(fd < 0)
|
||||
return;
|
||||
write(fd, &c, 1);
|
||||
}
|
||||
|
||||
void
|
||||
fe_svc(void)
|
||||
{
|
||||
u32 req;
|
||||
|
||||
req = h2f_fe[FEREG_REQ];
|
||||
|
||||
if(req & 1) svc_ptr();
|
||||
if(req & 2) svc_ptp();
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
init6(void)
|
||||
{
|
||||
if((memfd = open("/dev/mem", (O_RDWR | O_SYNC))) == -1) {
|
||||
fprintf(stderr, "ERROR: could not open /dev/mem...\n");
|
||||
exit(1);
|
||||
}
|
||||
virtual_base = (u32*)mmap(nil, PERIPH_SPAN,
|
||||
(PROT_READ | PROT_WRITE), MAP_SHARED, memfd, PERIPH_BASE);
|
||||
if(virtual_base == MAP_FAILED) {
|
||||
fprintf(stderr, "ERROR: mmap() failed...\n");
|
||||
close(memfd);
|
||||
exit(1);
|
||||
}
|
||||
h2f_base = (u64*)mmap(nil, 0x100000,
|
||||
(PROT_READ | PROT_WRITE), MAP_SHARED, memfd, H2F_BASE);
|
||||
if(h2f_base == MAP_FAILED) {
|
||||
fprintf(stderr, "ERROR: mmap() failed...\n");
|
||||
close(memfd);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
h2f_cmemif = getLWH2Faddr(0x10000);
|
||||
h2f_fmemif = getLWH2Faddr(0x10010);
|
||||
h2f_apr = getLWH2Faddr(0x10100);
|
||||
h2f_fe = getLWH2Faddr(0x20000);
|
||||
}
|
||||
|
||||
void
|
||||
deinit6(void)
|
||||
{
|
||||
if(munmap(virtual_base, PERIPH_SPAN) != 0) {
|
||||
fprintf(stderr, "ERROR: munmap() failed...\n");
|
||||
close(memfd);
|
||||
exit(1);
|
||||
}
|
||||
close(memfd);
|
||||
}
|
||||
33
fe6/ka/regs.h
Normal file
33
fe6/ka/regs.h
Normal file
@ -0,0 +1,33 @@
|
||||
#define PDP_REGS \
|
||||
X("DS", APR_DS)\
|
||||
X("AS", APR_AS)\
|
||||
X("RPT", APR_RPT)\
|
||||
X("IR", APR_IR)\
|
||||
X("MI", APR_MI)\
|
||||
X("PC", APR_PC)\
|
||||
X("MA", APR_MA)\
|
||||
X("PIH", APR_PIH)\
|
||||
X("PIR", APR_PIR)\
|
||||
X("PIO", APR_PIO)\
|
||||
X("RUN", APR_RUN)\
|
||||
X("PION", APR_PION)\
|
||||
X("STOP", APR_STOP)
|
||||
#ifdef TEST
|
||||
#define PDP_REGS_TEST \
|
||||
X("SW", APR_SW_DN)\
|
||||
X("SWU", APR_SW_UP)\
|
||||
X("MAINT", APR_MAINT_DN)\
|
||||
X("MAINTU", APR_MAINT_UP)\
|
||||
X("AR", APR_AR)\
|
||||
X("BR", APR_BR)\
|
||||
X("MQ", APR_MQ)\
|
||||
X("AD", APR_AD)\
|
||||
X("TTY.TTI", TTY_TTI)\
|
||||
X("TTY.ST", TTY_ST)\
|
||||
X("PTR.PTR", PTR_PTR)\
|
||||
X("PTR.ST", PTR_ST)\
|
||||
X("PTR.FE", PTR_FE)\
|
||||
X("FE.REQ", FE_REQ)
|
||||
#else
|
||||
#define PDP_REGS_TEST
|
||||
#endif
|
||||
@ -77,10 +77,10 @@ module apr(
|
||||
output wire [0:7] ff13,
|
||||
|
||||
// membus
|
||||
output wire membus_wr_rs,
|
||||
output wire membus_rq_cyc,
|
||||
output wire membus_rd_rq,
|
||||
output wire membus_wr_rq,
|
||||
output wire membus_rq_cyc,
|
||||
output wire membus_wr_rs,
|
||||
output wire [21:35] membus_ma,
|
||||
output wire [18:21] membus_sel,
|
||||
output wire membus_fmc_select,
|
||||
@ -98,10 +98,13 @@ module apr(
|
||||
output wire iobus_cono_set,
|
||||
output wire iobus_iob_fm_datai,
|
||||
output wire iobus_iob_fm_status,
|
||||
output wire iobus_rdi_pulse, // unused on 6
|
||||
output wire [3:9] iobus_ios,
|
||||
output wire [0:35] iobus_iob_out,
|
||||
input wire [1:7] iobus_pi_req,
|
||||
input wire [0:35] iobus_iob_in
|
||||
input wire [0:35] iobus_iob_in,
|
||||
input wire iobus_dr_split,
|
||||
input wire iobus_rdi_data // unused on 6
|
||||
);
|
||||
|
||||
`ifdef simulation
|
||||
@ -111,6 +114,7 @@ module apr(
|
||||
`endif
|
||||
wire rst = reset | ~sw_power;
|
||||
|
||||
assign iobus_rdi_pulse = 0;
|
||||
|
||||
assign ff0 = { key_ex_st, key_ex_sync, key_dep_st, key_dep_sync, key_rdwr, mc_rd, mc_wr, mc_rq };
|
||||
assign ff1 = { if1a, af0, af3, af3a, et4_ar_pse, f1a, f4a, f6a };
|
||||
@ -2846,7 +2850,7 @@ module apr(
|
||||
// reg mc_stop;
|
||||
reg mc_stop_sync;
|
||||
reg mc_split_cyc_sync;
|
||||
wire mc_dr_split = 0; // we don't support drums right now
|
||||
wire mc_dr_split = iobus_dr_split;
|
||||
wire mc_sw_stop = key_mem_stop | sw_addr_stop | mc_dr_split;
|
||||
wire mc_rd_rq_pulse;
|
||||
wire mc_wr_rq_pulse;
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
|
||||
module dly50ns(input clk, input reset, input in, output p);
|
||||
reg [2-1:0] r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
@ -13,6 +14,7 @@ module dly50ns(input clk, input reset, input in, output p);
|
||||
assign p = r == 2;
|
||||
endmodule
|
||||
|
||||
|
||||
module dly70ns(input clk, input reset, input in, output p);
|
||||
reg [2-1:0] r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
@ -28,6 +30,7 @@ module dly70ns(input clk, input reset, input in, output p);
|
||||
assign p = r == 3;
|
||||
endmodule
|
||||
|
||||
|
||||
module dly100ns(input clk, input reset, input in, output p);
|
||||
reg [3-1:0] r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
@ -43,6 +46,7 @@ module dly100ns(input clk, input reset, input in, output p);
|
||||
assign p = r == 5;
|
||||
endmodule
|
||||
|
||||
|
||||
module dly150ns(input clk, input reset, input in, output p);
|
||||
reg [3-1:0] r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
@ -58,6 +62,7 @@ module dly150ns(input clk, input reset, input in, output p);
|
||||
assign p = r == 7;
|
||||
endmodule
|
||||
|
||||
|
||||
module dly200ns(input clk, input reset, input in, output p);
|
||||
reg [4-1:0] r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
@ -73,6 +78,7 @@ module dly200ns(input clk, input reset, input in, output p);
|
||||
assign p = r == 10;
|
||||
endmodule
|
||||
|
||||
|
||||
module dly250ns(input clk, input reset, input in, output p);
|
||||
reg [4-1:0] r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
@ -88,6 +94,7 @@ module dly250ns(input clk, input reset, input in, output p);
|
||||
assign p = r == 12;
|
||||
endmodule
|
||||
|
||||
|
||||
module dly300ns(input clk, input reset, input in, output p);
|
||||
reg [4-1:0] r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
@ -103,6 +110,7 @@ module dly300ns(input clk, input reset, input in, output p);
|
||||
assign p = r == 15;
|
||||
endmodule
|
||||
|
||||
|
||||
module dly400ns(input clk, input reset, input in, output p);
|
||||
reg [5-1:0] r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
@ -118,6 +126,7 @@ module dly400ns(input clk, input reset, input in, output p);
|
||||
assign p = r == 20;
|
||||
endmodule
|
||||
|
||||
|
||||
module dly450ns(input clk, input reset, input in, output p);
|
||||
reg [5-1:0] r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
@ -133,6 +142,7 @@ module dly450ns(input clk, input reset, input in, output p);
|
||||
assign p = r == 22;
|
||||
endmodule
|
||||
|
||||
|
||||
module dly550ns(input clk, input reset, input in, output p);
|
||||
reg [5-1:0] r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
@ -148,6 +158,7 @@ module dly550ns(input clk, input reset, input in, output p);
|
||||
assign p = r == 27;
|
||||
endmodule
|
||||
|
||||
|
||||
module dly750ns(input clk, input reset, input in, output p);
|
||||
reg [6-1:0] r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
@ -163,6 +174,7 @@ module dly750ns(input clk, input reset, input in, output p);
|
||||
assign p = r == 37;
|
||||
endmodule
|
||||
|
||||
|
||||
module dly800ns(input clk, input reset, input in, output p);
|
||||
reg [6-1:0] r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
|
||||
@ -4,101 +4,6 @@ from math import *
|
||||
# delays are rounded down
|
||||
clock=20 # cycle time of clock in ns
|
||||
|
||||
nsdly="""module dly{ns}ns(input clk, input reset, input in, output p);
|
||||
reg [{width}-1:0] r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if(reset)
|
||||
r <= 0;
|
||||
else begin
|
||||
if(r)
|
||||
r <= r + {width}'b1;
|
||||
if(in)
|
||||
r <= 1;
|
||||
end
|
||||
end
|
||||
assign p = r == {n};
|
||||
endmodule
|
||||
"""
|
||||
|
||||
def gendlyns(ns):
|
||||
n = ns//clock
|
||||
nb = ceil(log(n+1,2))
|
||||
print(nsdly.format(ns=ns, width=nb, n=n))
|
||||
|
||||
gendlyns(50)
|
||||
gendlyns(70)
|
||||
gendlyns(100)
|
||||
gendlyns(150)
|
||||
gendlyns(200)
|
||||
gendlyns(250)
|
||||
gendlyns(300)
|
||||
gendlyns(400)
|
||||
gendlyns(450)
|
||||
gendlyns(550)
|
||||
gendlyns(750)
|
||||
gendlyns(800)
|
||||
|
||||
|
||||
usdly="""
|
||||
module dly{us}us(input clk, input reset, input in, output p);
|
||||
reg [{width}-1:0] r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if(reset)
|
||||
r <= 0;
|
||||
else begin
|
||||
if(r)
|
||||
r <= r + {width}'b1;
|
||||
if(in)
|
||||
r <= 1;
|
||||
end
|
||||
end
|
||||
assign p = r == {n};
|
||||
endmodule
|
||||
"""
|
||||
|
||||
usldly="""
|
||||
module ldly{us}us(input clk, input reset, input in, output p, output reg l);
|
||||
reg [{width}-1:0] r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if(reset) begin
|
||||
r <= 0;
|
||||
l <= 0;
|
||||
end else begin
|
||||
if(r)
|
||||
r <= r + {width}'b1;
|
||||
if(in) begin
|
||||
r <= 1;
|
||||
l <= 1;
|
||||
end
|
||||
if(p) begin
|
||||
r <= 0;
|
||||
l <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
assign p = r == {n};
|
||||
endmodule
|
||||
"""
|
||||
|
||||
def genldlyus(us):
|
||||
s = str(us).replace('.', '_')
|
||||
n = int(us*1000//clock)
|
||||
nb = ceil(log(n+1,2))
|
||||
print(usldly.format(us=s, width=nb, n=n))
|
||||
|
||||
def gendlyus(us):
|
||||
s = str(us).replace('.', '_')
|
||||
n = int(us*1000//clock)
|
||||
nb = ceil(log(n+1,2))
|
||||
print(usdly.format(us=s, width=nb, n=n))
|
||||
|
||||
gendlyus(1)
|
||||
genldlyus(1)
|
||||
genldlyus(1.5)
|
||||
genldlyus(2)
|
||||
gendlyus(100)
|
||||
genldlyus(100)
|
||||
|
||||
|
||||
dly="""
|
||||
module dly{type}(input clk, input reset, input in, output p);
|
||||
@ -141,6 +46,24 @@ module ldly{type}(input clk, input reset, input in, output p, output reg l);
|
||||
endmodule
|
||||
"""
|
||||
|
||||
def gendlyns(ns):
|
||||
t = str(ns).replace('.', '_')
|
||||
n = int(ns//clock)
|
||||
nb = ceil(log(n+1,2))
|
||||
print(dly.format(type='%sns' % t, width=nb, n=n))
|
||||
|
||||
def gendlyus(us):
|
||||
t = str(us).replace('.', '_')
|
||||
n = int(us*1000//clock)
|
||||
nb = ceil(log(n+1,2))
|
||||
print(dly.format(type='%sus' % t, width=nb, n=n))
|
||||
|
||||
def genldlyus(us):
|
||||
t = str(us).replace('.', '_')
|
||||
n = int(us*1000//clock)
|
||||
nb = ceil(log(n+1,2))
|
||||
print(ldly.format(type='%sus' % t, width=nb, n=n))
|
||||
|
||||
def gendlyms(ms):
|
||||
t = str(ms).replace('.', '_')
|
||||
n = int(ms*1000*1000//clock)
|
||||
@ -160,10 +83,34 @@ def genldlys(s):
|
||||
print(ldly.format(type='%ss' % t, width=nb, n=n))
|
||||
|
||||
|
||||
|
||||
gendlyns(50)
|
||||
gendlyns(70)
|
||||
gendlyns(100)
|
||||
gendlyns(150)
|
||||
gendlyns(200)
|
||||
gendlyns(250)
|
||||
gendlyns(300)
|
||||
gendlyns(400)
|
||||
gendlyns(450)
|
||||
gendlyns(550)
|
||||
gendlyns(750)
|
||||
gendlyns(800)
|
||||
|
||||
|
||||
gendlyus(1)
|
||||
genldlyus(1)
|
||||
genldlyus(1.5)
|
||||
genldlyus(2)
|
||||
gendlyus(100)
|
||||
genldlyus(100)
|
||||
|
||||
|
||||
gendlyms(2.1)
|
||||
gendlyms(2.5)
|
||||
gendlyms(5)
|
||||
genldlyms(5)
|
||||
|
||||
|
||||
genldlys(1)
|
||||
genldlys(5)
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
// AUTOGEN
|
||||
module iobus_0_connect(
|
||||
// unused
|
||||
input wire clk,
|
||||
@ -12,11 +13,17 @@ module iobus_0_connect(
|
||||
input wire m_cono_set,
|
||||
input wire m_iob_fm_datai,
|
||||
input wire m_iob_fm_status,
|
||||
input wire [3:9] m_ios,
|
||||
input wire [0:35] m_iob_out,
|
||||
output wire [1:7] m_pi_req,
|
||||
output wire [0:35] m_iob_in
|
||||
input wire m_rdi_pulse,
|
||||
input wire [3:9] m_ios,
|
||||
input wire [0:35] m_iob_write,
|
||||
output wire [1:7] m_pi_req,
|
||||
output wire [0:35] m_iob_read,
|
||||
output wire m_dr_split,
|
||||
output wire m_rdi_data
|
||||
);
|
||||
assign m_pi_req = 0;
|
||||
assign m_iob_in = m_iob_out;
|
||||
assign m_iob_read = m_iob_write;
|
||||
assign m_dr_split = 0;
|
||||
assign m_rdi_data = 0;
|
||||
|
||||
endmodule
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
// AUTOGEN
|
||||
module iobus_1_connect(
|
||||
// unused
|
||||
input wire clk,
|
||||
@ -12,10 +13,13 @@ module iobus_1_connect(
|
||||
input wire m_cono_set,
|
||||
input wire m_iob_fm_datai,
|
||||
input wire m_iob_fm_status,
|
||||
input wire m_rdi_pulse,
|
||||
input wire [3:9] m_ios,
|
||||
input wire [0:35] m_iob_write,
|
||||
output wire [1:7] m_pi_req,
|
||||
output wire [0:35] m_iob_read,
|
||||
output wire m_dr_split,
|
||||
output wire m_rdi_data,
|
||||
|
||||
// Slave 0
|
||||
output wire s0_iob_poweron,
|
||||
@ -26,13 +30,19 @@ module iobus_1_connect(
|
||||
output wire s0_cono_set,
|
||||
output wire s0_iob_fm_datai,
|
||||
output wire s0_iob_fm_status,
|
||||
output wire s0_rdi_pulse,
|
||||
output wire [3:9] s0_ios,
|
||||
output wire [0:35] s0_iob_write,
|
||||
input wire [1:7] s0_pi_req,
|
||||
input wire [0:35] s0_iob_read
|
||||
input wire [0:35] s0_iob_read,
|
||||
input wire s0_dr_split,
|
||||
input wire s0_rdi_data
|
||||
);
|
||||
assign m_pi_req = s0_pi_req;
|
||||
assign m_pi_req = 0 | s0_pi_req;
|
||||
assign m_iob_read = m_iob_write | s0_iob_read;
|
||||
assign m_dr_split = 0 | s0_dr_split;
|
||||
assign m_rdi_data = 0 | s0_rdi_data;
|
||||
|
||||
|
||||
assign s0_iob_poweron = m_iob_poweron;
|
||||
assign s0_iob_reset = m_iob_reset;
|
||||
@ -42,6 +52,7 @@ module iobus_1_connect(
|
||||
assign s0_cono_set = m_cono_set;
|
||||
assign s0_iob_fm_datai = m_iob_fm_datai;
|
||||
assign s0_iob_fm_status = m_iob_fm_status;
|
||||
assign s0_rdi_pulse = m_rdi_pulse;
|
||||
assign s0_ios = m_ios;
|
||||
assign s0_iob_write = m_iob_write;
|
||||
endmodule
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
// AUTOGEN
|
||||
module iobus_2_connect(
|
||||
// unused
|
||||
input wire clk,
|
||||
@ -12,10 +13,13 @@ module iobus_2_connect(
|
||||
input wire m_cono_set,
|
||||
input wire m_iob_fm_datai,
|
||||
input wire m_iob_fm_status,
|
||||
input wire m_rdi_pulse,
|
||||
input wire [3:9] m_ios,
|
||||
input wire [0:35] m_iob_write,
|
||||
output wire [1:7] m_pi_req,
|
||||
output wire [0:35] m_iob_read,
|
||||
output wire m_dr_split,
|
||||
output wire m_rdi_data,
|
||||
|
||||
// Slave 0
|
||||
output wire s0_iob_poweron,
|
||||
@ -26,12 +30,15 @@ module iobus_2_connect(
|
||||
output wire s0_cono_set,
|
||||
output wire s0_iob_fm_datai,
|
||||
output wire s0_iob_fm_status,
|
||||
output wire s0_rdi_pulse,
|
||||
output wire [3:9] s0_ios,
|
||||
output wire [0:35] s0_iob_write,
|
||||
input wire [1:7] s0_pi_req,
|
||||
input wire [0:35] s0_iob_read,
|
||||
input wire s0_dr_split,
|
||||
input wire s0_rdi_data,
|
||||
|
||||
// Slave
|
||||
// Slave 1
|
||||
output wire s1_iob_poweron,
|
||||
output wire s1_iob_reset,
|
||||
output wire s1_datao_clear,
|
||||
@ -40,13 +47,19 @@ module iobus_2_connect(
|
||||
output wire s1_cono_set,
|
||||
output wire s1_iob_fm_datai,
|
||||
output wire s1_iob_fm_status,
|
||||
output wire s1_rdi_pulse,
|
||||
output wire [3:9] s1_ios,
|
||||
output wire [0:35] s1_iob_write,
|
||||
input wire [1:7] s1_pi_req,
|
||||
input wire [0:35] s1_iob_read
|
||||
input wire [0:35] s1_iob_read,
|
||||
input wire s1_dr_split,
|
||||
input wire s1_rdi_data
|
||||
);
|
||||
assign m_pi_req = s0_pi_req | s1_pi_req;
|
||||
assign m_pi_req = 0 | s0_pi_req | s1_pi_req;
|
||||
assign m_iob_read = m_iob_write | s0_iob_read | s1_iob_read;
|
||||
assign m_dr_split = 0 | s0_dr_split | s1_dr_split;
|
||||
assign m_rdi_data = 0 | s0_rdi_data | s1_rdi_data;
|
||||
|
||||
|
||||
assign s0_iob_poweron = m_iob_poweron;
|
||||
assign s0_iob_reset = m_iob_reset;
|
||||
@ -56,6 +69,7 @@ module iobus_2_connect(
|
||||
assign s0_cono_set = m_cono_set;
|
||||
assign s0_iob_fm_datai = m_iob_fm_datai;
|
||||
assign s0_iob_fm_status = m_iob_fm_status;
|
||||
assign s0_rdi_pulse = m_rdi_pulse;
|
||||
assign s0_ios = m_ios;
|
||||
assign s0_iob_write = m_iob_write;
|
||||
|
||||
@ -67,6 +81,7 @@ module iobus_2_connect(
|
||||
assign s1_cono_set = m_cono_set;
|
||||
assign s1_iob_fm_datai = m_iob_fm_datai;
|
||||
assign s1_iob_fm_status = m_iob_fm_status;
|
||||
assign s1_rdi_pulse = m_rdi_pulse;
|
||||
assign s1_ios = m_ios;
|
||||
assign s1_iob_write = m_iob_write;
|
||||
endmodule
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
// AUTOGEN
|
||||
module iobus_3_connect(
|
||||
// unused
|
||||
input wire clk,
|
||||
@ -12,10 +13,13 @@ module iobus_3_connect(
|
||||
input wire m_cono_set,
|
||||
input wire m_iob_fm_datai,
|
||||
input wire m_iob_fm_status,
|
||||
input wire m_rdi_pulse,
|
||||
input wire [3:9] m_ios,
|
||||
input wire [0:35] m_iob_write,
|
||||
output wire [1:7] m_pi_req,
|
||||
output wire [0:35] m_iob_read,
|
||||
output wire m_dr_split,
|
||||
output wire m_rdi_data,
|
||||
|
||||
// Slave 0
|
||||
output wire s0_iob_poweron,
|
||||
@ -26,10 +30,13 @@ module iobus_3_connect(
|
||||
output wire s0_cono_set,
|
||||
output wire s0_iob_fm_datai,
|
||||
output wire s0_iob_fm_status,
|
||||
output wire s0_rdi_pulse,
|
||||
output wire [3:9] s0_ios,
|
||||
output wire [0:35] s0_iob_write,
|
||||
input wire [1:7] s0_pi_req,
|
||||
input wire [0:35] s0_iob_read,
|
||||
input wire s0_dr_split,
|
||||
input wire s0_rdi_data,
|
||||
|
||||
// Slave 1
|
||||
output wire s1_iob_poweron,
|
||||
@ -40,10 +47,13 @@ module iobus_3_connect(
|
||||
output wire s1_cono_set,
|
||||
output wire s1_iob_fm_datai,
|
||||
output wire s1_iob_fm_status,
|
||||
output wire s1_rdi_pulse,
|
||||
output wire [3:9] s1_ios,
|
||||
output wire [0:35] s1_iob_write,
|
||||
input wire [1:7] s1_pi_req,
|
||||
input wire [0:35] s1_iob_read,
|
||||
input wire s1_dr_split,
|
||||
input wire s1_rdi_data,
|
||||
|
||||
// Slave 2
|
||||
output wire s2_iob_poweron,
|
||||
@ -54,13 +64,19 @@ module iobus_3_connect(
|
||||
output wire s2_cono_set,
|
||||
output wire s2_iob_fm_datai,
|
||||
output wire s2_iob_fm_status,
|
||||
output wire s2_rdi_pulse,
|
||||
output wire [3:9] s2_ios,
|
||||
output wire [0:35] s2_iob_write,
|
||||
input wire [1:7] s2_pi_req,
|
||||
input wire [0:35] s2_iob_read
|
||||
input wire [0:35] s2_iob_read,
|
||||
input wire s2_dr_split,
|
||||
input wire s2_rdi_data
|
||||
);
|
||||
assign m_pi_req = s0_pi_req | s1_pi_req | s2_pi_req;
|
||||
assign m_pi_req = 0 | s0_pi_req | s1_pi_req | s2_pi_req;
|
||||
assign m_iob_read = m_iob_write | s0_iob_read | s1_iob_read | s2_iob_read;
|
||||
assign m_dr_split = 0 | s0_dr_split | s1_dr_split | s2_dr_split;
|
||||
assign m_rdi_data = 0 | s0_rdi_data | s1_rdi_data | s2_rdi_data;
|
||||
|
||||
|
||||
assign s0_iob_poweron = m_iob_poweron;
|
||||
assign s0_iob_reset = m_iob_reset;
|
||||
@ -70,6 +86,7 @@ module iobus_3_connect(
|
||||
assign s0_cono_set = m_cono_set;
|
||||
assign s0_iob_fm_datai = m_iob_fm_datai;
|
||||
assign s0_iob_fm_status = m_iob_fm_status;
|
||||
assign s0_rdi_pulse = m_rdi_pulse;
|
||||
assign s0_ios = m_ios;
|
||||
assign s0_iob_write = m_iob_write;
|
||||
|
||||
@ -81,6 +98,7 @@ module iobus_3_connect(
|
||||
assign s1_cono_set = m_cono_set;
|
||||
assign s1_iob_fm_datai = m_iob_fm_datai;
|
||||
assign s1_iob_fm_status = m_iob_fm_status;
|
||||
assign s1_rdi_pulse = m_rdi_pulse;
|
||||
assign s1_ios = m_ios;
|
||||
assign s1_iob_write = m_iob_write;
|
||||
|
||||
@ -92,6 +110,7 @@ module iobus_3_connect(
|
||||
assign s2_cono_set = m_cono_set;
|
||||
assign s2_iob_fm_datai = m_iob_fm_datai;
|
||||
assign s2_iob_fm_status = m_iob_fm_status;
|
||||
assign s2_rdi_pulse = m_rdi_pulse;
|
||||
assign s2_ios = m_ios;
|
||||
assign s2_iob_write = m_iob_write;
|
||||
endmodule
|
||||
|
||||
46
verilog/membus_1_connect.v
Normal file
46
verilog/membus_1_connect.v
Normal file
@ -0,0 +1,46 @@
|
||||
module membus_1_connect(
|
||||
// unused
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
|
||||
// Master
|
||||
input wire m_wr_rs,
|
||||
input wire m_rq_cyc,
|
||||
input wire m_rd_rq,
|
||||
input wire m_wr_rq,
|
||||
input wire [21:35] m_ma,
|
||||
input wire [18:21] m_sel,
|
||||
input wire m_fmc_select,
|
||||
input wire [0:35] m_mb_write,
|
||||
output wire m_addr_ack,
|
||||
output wire m_rd_rs,
|
||||
output wire [0:35] m_mb_read,
|
||||
|
||||
// Slave 0
|
||||
output wire s0_wr_rs,
|
||||
output wire s0_rq_cyc,
|
||||
output wire s0_rd_rq,
|
||||
output wire s0_wr_rq,
|
||||
output wire [21:35] s0_ma,
|
||||
output wire [18:21] s0_sel,
|
||||
output wire s0_fmc_select,
|
||||
output wire [0:35] s0_mb_write,
|
||||
input wire s0_addr_ack,
|
||||
input wire s0_rd_rs,
|
||||
input wire [0:35] s0_mb_read
|
||||
);
|
||||
wire [0:35] mb_out = m_mb_write | s0_mb_read;
|
||||
|
||||
assign m_addr_ack = s0_addr_ack;
|
||||
assign m_rd_rs = s0_rd_rs;
|
||||
assign m_mb_read = mb_out;
|
||||
|
||||
assign s0_wr_rs = m_wr_rs;
|
||||
assign s0_rq_cyc = m_rq_cyc;
|
||||
assign s0_rd_rq = m_rd_rq;
|
||||
assign s0_wr_rq = m_wr_rq;
|
||||
assign s0_ma = m_ma;
|
||||
assign s0_sel = m_sel;
|
||||
assign s0_fmc_select = m_fmc_select;
|
||||
assign s0_mb_write = mb_out;
|
||||
endmodule
|
||||
217
verilog/mkiocon.py
Executable file
217
verilog/mkiocon.py
Executable file
@ -0,0 +1,217 @@
|
||||
#!/usr/bin/python3
|
||||
|
||||
import sys;
|
||||
|
||||
|
||||
start = '''// AUTOGEN
|
||||
module iobus_{num}_connect(
|
||||
// unused
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
|
||||
// Master
|
||||
input wire m_iob_poweron,
|
||||
input wire m_iob_reset,
|
||||
input wire m_datao_clear,
|
||||
input wire m_datao_set,
|
||||
input wire m_cono_clear,
|
||||
input wire m_cono_set,
|
||||
input wire m_iob_fm_datai,
|
||||
input wire m_iob_fm_status,
|
||||
input wire m_rdi_pulse,
|
||||
input wire [3:9] m_ios,
|
||||
input wire [0:35] m_iob_write,
|
||||
output wire [1:7] m_pi_req,
|
||||
output wire [0:35] m_iob_read,
|
||||
output wire m_dr_split,
|
||||
output wire m_rdi_data'''
|
||||
|
||||
slv = ''',
|
||||
|
||||
// Slave {i}
|
||||
output wire s{i}_iob_poweron,
|
||||
output wire s{i}_iob_reset,
|
||||
output wire s{i}_datao_clear,
|
||||
output wire s{i}_datao_set,
|
||||
output wire s{i}_cono_clear,
|
||||
output wire s{i}_cono_set,
|
||||
output wire s{i}_iob_fm_datai,
|
||||
output wire s{i}_iob_fm_status,
|
||||
output wire s{i}_rdi_pulse,
|
||||
output wire [3:9] s{i}_ios,
|
||||
output wire [0:35] s{i}_iob_write,
|
||||
input wire [1:7] s{i}_pi_req,
|
||||
input wire [0:35] s{i}_iob_read,
|
||||
input wire s{i}_dr_split,
|
||||
input wire s{i}_rdi_data'''
|
||||
|
||||
mas = '''
|
||||
);
|
||||
assign m_pi_req = {pireq};
|
||||
assign m_iob_read = {read};
|
||||
assign m_dr_split = {split};
|
||||
assign m_rdi_data = {rdidata};
|
||||
'''
|
||||
|
||||
sas = '''
|
||||
assign s{i}_iob_poweron = m_iob_poweron;
|
||||
assign s{i}_iob_reset = m_iob_reset;
|
||||
assign s{i}_datao_clear = m_datao_clear;
|
||||
assign s{i}_datao_set = m_datao_set;
|
||||
assign s{i}_cono_clear = m_cono_clear;
|
||||
assign s{i}_cono_set = m_cono_set;
|
||||
assign s{i}_iob_fm_datai = m_iob_fm_datai;
|
||||
assign s{i}_iob_fm_status = m_iob_fm_status;
|
||||
assign s{i}_rdi_pulse = m_rdi_pulse;
|
||||
assign s{i}_ios = m_ios;
|
||||
assign s{i}_iob_write = m_iob_write;'''
|
||||
|
||||
n = int(sys.argv[1])
|
||||
|
||||
vf = open("iobus_%d_connect.v" % n, "w+")
|
||||
tf = open("iobus_%d_connect_hw.tcl" % n, "w+")
|
||||
|
||||
sys.stdout = vf
|
||||
|
||||
print(start.format(num=n), end='')
|
||||
for i in range(n):
|
||||
print(slv.format(i=i), end='')
|
||||
|
||||
pireq = ' | '.join(['0'] + ["s%d_pi_req" % i for i in range(n)])
|
||||
read = ' | '.join(['m_iob_write'] + ["s%d_iob_read" % i for i in range(n)])
|
||||
split = ' | '.join(['0'] + ["s%d_dr_split" % i for i in range(n)])
|
||||
rdidata = ' | '.join(['0'] + ["s%d_rdi_data" % i for i in range(n)])
|
||||
|
||||
print(mas.format(pireq=pireq, read=read, split=split, rdidata=rdidata))
|
||||
|
||||
for i in range(n):
|
||||
print(sas.format(i=i))
|
||||
|
||||
print('endmodule')
|
||||
|
||||
|
||||
|
||||
|
||||
tclhead='''package require -exact qsys 16.1
|
||||
|
||||
|
||||
#
|
||||
# module iobus_{n}_connect
|
||||
#
|
||||
set_module_property DESCRIPTION ""
|
||||
set_module_property NAME iobus_{n}_connect
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property INTERNAL false
|
||||
set_module_property OPAQUE_ADDRESS_MAP true
|
||||
set_module_property AUTHOR ""
|
||||
set_module_property DISPLAY_NAME iobus_{n}_connect
|
||||
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
|
||||
set_module_property EDITABLE true
|
||||
set_module_property REPORT_TO_TALKBACK false
|
||||
set_module_property ALLOW_GREYBOX_GENERATION false
|
||||
set_module_property REPORT_HIERARCHY false
|
||||
|
||||
#
|
||||
# file sets
|
||||
#
|
||||
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
|
||||
set_fileset_property QUARTUS_SYNTH TOP_LEVEL iobus_{n}_connect
|
||||
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
|
||||
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
|
||||
add_fileset_file iobus_{n}_connect.v VERILOG PATH rtl/iobus_{n}_connect.v TOP_LEVEL_FILE
|
||||
|
||||
#
|
||||
# connection point clock
|
||||
#
|
||||
add_interface clock clock end
|
||||
set_interface_property clock clockRate 0
|
||||
set_interface_property clock ENABLED true
|
||||
set_interface_property clock EXPORT_OF ""
|
||||
set_interface_property clock PORT_NAME_MAP ""
|
||||
set_interface_property clock CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property clock SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port clock clk clk Input 1
|
||||
|
||||
|
||||
#
|
||||
# connection point reset
|
||||
#
|
||||
add_interface reset reset end
|
||||
set_interface_property reset associatedClock clock
|
||||
set_interface_property reset synchronousEdges DEASSERT
|
||||
set_interface_property reset ENABLED true
|
||||
set_interface_property reset EXPORT_OF ""
|
||||
set_interface_property reset PORT_NAME_MAP ""
|
||||
set_interface_property reset CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property reset SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port reset reset reset Input 1
|
||||
|
||||
'''
|
||||
|
||||
tclslv='''#
|
||||
# connection point iobus_slave{i}
|
||||
#
|
||||
add_interface iobus_slave{i} conduit end
|
||||
set_interface_property iobus_slave{i} associatedClock clock
|
||||
set_interface_property iobus_slave{i} associatedReset reset
|
||||
set_interface_property iobus_slave{i} ENABLED true
|
||||
set_interface_property iobus_slave{i} EXPORT_OF ""
|
||||
set_interface_property iobus_slave{i} PORT_NAME_MAP ""
|
||||
set_interface_property iobus_slave{i} CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property iobus_slave{i} SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port iobus_slave{i} s{i}_iob_poweron iob_poweron Output 1
|
||||
add_interface_port iobus_slave{i} s{i}_iob_reset iob_reset Output 1
|
||||
add_interface_port iobus_slave{i} s{i}_datao_clear datao_clear Output 1
|
||||
add_interface_port iobus_slave{i} s{i}_datao_set datao_set Output 1
|
||||
add_interface_port iobus_slave{i} s{i}_cono_clear cono_clear Output 1
|
||||
add_interface_port iobus_slave{i} s{i}_cono_set cono_set Output 1
|
||||
add_interface_port iobus_slave{i} s{i}_iob_fm_datai iob_fm_datai Output 1
|
||||
add_interface_port iobus_slave{i} s{i}_iob_fm_status iob_fm_status Output 1
|
||||
add_interface_port iobus_slave{i} s{i}_rdi_pulse rdi_pulse Output 1
|
||||
add_interface_port iobus_slave{i} s{i}_ios ios Output 7
|
||||
add_interface_port iobus_slave{i} s{i}_iob_write iob_write Output 36
|
||||
add_interface_port iobus_slave{i} s{i}_pi_req pi_req Input 7
|
||||
add_interface_port iobus_slave{i} s{i}_iob_read iob_read Input 36
|
||||
add_interface_port iobus_slave{i} s{i}_dr_split dr_split Input 1
|
||||
add_interface_port iobus_slave{i} s{i}_rdi_data rdi_data Input 1
|
||||
|
||||
'''
|
||||
|
||||
tclmas='''#
|
||||
# connection point iobus_master
|
||||
#
|
||||
add_interface iobus_master conduit end
|
||||
set_interface_property iobus_master associatedClock clock
|
||||
set_interface_property iobus_master associatedReset reset
|
||||
set_interface_property iobus_master ENABLED true
|
||||
set_interface_property iobus_master EXPORT_OF ""
|
||||
set_interface_property iobus_master PORT_NAME_MAP ""
|
||||
set_interface_property iobus_master CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property iobus_master SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port iobus_master m_iob_poweron iob_poweron Input 1
|
||||
add_interface_port iobus_master m_iob_reset iob_reset Input 1
|
||||
add_interface_port iobus_master m_datao_clear datao_clear Input 1
|
||||
add_interface_port iobus_master m_datao_set datao_set Input 1
|
||||
add_interface_port iobus_master m_cono_clear cono_clear Input 1
|
||||
add_interface_port iobus_master m_cono_set cono_set Input 1
|
||||
add_interface_port iobus_master m_iob_fm_datai iob_fm_datai Input 1
|
||||
add_interface_port iobus_master m_iob_fm_status iob_fm_status Input 1
|
||||
add_interface_port iobus_master m_rdi_pulse rdi_pulse Input 1
|
||||
add_interface_port iobus_master m_ios ios Input 7
|
||||
add_interface_port iobus_master m_iob_write iob_write Input 36
|
||||
add_interface_port iobus_master m_pi_req pi_req Output 7
|
||||
add_interface_port iobus_master m_iob_read iob_read Output 36
|
||||
add_interface_port iobus_master m_dr_split dr_split Output 1
|
||||
add_interface_port iobus_master m_rdi_data rdi_data Output 1
|
||||
|
||||
'''
|
||||
|
||||
sys.stdout = tf
|
||||
print(tclhead.format(n=n))
|
||||
for i in range(n):
|
||||
print(tclslv.format(i=i))
|
||||
print(tclmas)
|
||||
@ -11,10 +11,13 @@ module ptp(
|
||||
input wire iobus_cono_set,
|
||||
input wire iobus_iob_fm_datai,
|
||||
input wire iobus_iob_fm_status,
|
||||
input wire iobus_rdi_pulse, // unused on 6
|
||||
input wire [3:9] iobus_ios,
|
||||
input wire [0:35] iobus_iob_in,
|
||||
output wire [1:7] iobus_pi_req,
|
||||
output wire [0:35] iobus_iob_out,
|
||||
output wire iobus_dr_split,
|
||||
output wire iobus_rdi_data, // unused on 6
|
||||
|
||||
/* Console panel */
|
||||
input wire key_tape_feed,
|
||||
@ -27,6 +30,9 @@ module ptp(
|
||||
|
||||
output wire fe_data_rq
|
||||
);
|
||||
assign iobus_dr_split = 0;
|
||||
assign iobus_rdi_data = 0;
|
||||
|
||||
assign ptp_ind = ptp;
|
||||
assign status_ind = { ptp_speed, ptp_b, ptp_busy, ptp_flag, ptp_pia };
|
||||
|
||||
|
||||
@ -11,10 +11,13 @@ module ptr(
|
||||
input wire iobus_cono_set,
|
||||
input wire iobus_iob_fm_datai,
|
||||
input wire iobus_iob_fm_status,
|
||||
input wire iobus_rdi_pulse, // unused on 6
|
||||
input wire [3:9] iobus_ios,
|
||||
input wire [0:35] iobus_iob_in,
|
||||
output wire [1:7] iobus_pi_req,
|
||||
output wire [0:35] iobus_iob_out,
|
||||
output wire iobus_dr_split,
|
||||
output wire iobus_rdi_data, // unused on 6
|
||||
|
||||
/* Console panel */
|
||||
input wire key_start,
|
||||
@ -29,6 +32,9 @@ module ptr(
|
||||
|
||||
output wire fe_data_rq
|
||||
);
|
||||
assign iobus_dr_split = 0;
|
||||
assign iobus_rdi_data = 0;
|
||||
|
||||
assign ptr_ind = ptr;
|
||||
assign status_ind = { motor_on, ptr_b, ptr_busy, ptr_flag, ptr_pia };
|
||||
|
||||
|
||||
@ -11,10 +11,13 @@ module tty(
|
||||
input wire iobus_cono_set,
|
||||
input wire iobus_iob_fm_datai,
|
||||
input wire iobus_iob_fm_status,
|
||||
input wire iobus_rdi_pulse, // unused on 6
|
||||
input wire [3:9] iobus_ios,
|
||||
input wire [0:35] iobus_iob_in,
|
||||
output wire [1:7] iobus_pi_req,
|
||||
output wire [0:35] iobus_iob_out,
|
||||
output wire iobus_dr_split,
|
||||
output wire iobus_rdi_data, // unused on 6
|
||||
|
||||
/* UART pins */
|
||||
input wire rx,
|
||||
@ -24,6 +27,9 @@ module tty(
|
||||
output wire [7:0] tti_ind,
|
||||
output wire [6:0] status_ind
|
||||
);
|
||||
assign iobus_dr_split = 0;
|
||||
assign iobus_rdi_data = 0;
|
||||
|
||||
wire clk2;
|
||||
clk14khz clock2(.inclk(clk),
|
||||
.outclk(clk2));
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user