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some more AR stuff
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aap
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@ -693,8 +693,7 @@ module apr(
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wire memac_ac = memac & ~ir[5];
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wire accp_etc_cond = ir_accp_OR_memac & ir[8] & ar0_xor_ar_ov |
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ir[7] & ar_eq_0;
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// simplifies to: accp_etc_cond != ir[6]
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wire accp_etal_test = (accp_etc_cond | ir[6]) & (~accp_etc_cond | ~ir[6]);
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wire accp_etal_test = accp_etc_cond ^ ir[6];
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wire accp_dir = accp & ir[5];
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/* ACBM */
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@ -1074,17 +1073,21 @@ module apr(
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wire ar_as_t1;
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wire ar_as_t2;
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wire ar_t3;
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wire ar_eq_fp_half = 0;
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wire ar_eq_0 = ar == 0;
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wire ar0_xor_ar1 = 0;
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wire ar_ov_set = 0;
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wire ar_cry0_xor_cry1 = 0;
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wire ar0_xor_ar_ov = 0;
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wire ar0_xor_mb0 = 0;
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wire ar0_eq_sc0 = 0;
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wire ar_flag_clr = mr_start | et0 & ir_jrst & ir[11];
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wire ar_flag_set = 0;
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wire ar_jfcl_clr = 0;
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wire ar_jrst_AND_ir11 = ir_jrst & ir[11];
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wire ar_flag_set = et1 & ar_jrst_AND_ir11;
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wire ar_jfcl_clr = et10 & ir_jfcl;
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wire ar_eq_fp_half = ar == 36'o000400000000;
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wire ar_eq_0 = ar == 0;
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wire ar0_xor_ar1 = ar[0] ^ ar[1];
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wire ar_ov_set = ar_cry0 ^ ar_cry1;
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wire ar_cry0_xor_cry1 = ar_ov_set & ~memac;
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wire ar0_xor_ar_ov = ar[0] ^ ar_cry0_xor_cry1;
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wire ar0_xor_mb0 = ar[0] ^ mb[0];
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wire ar0_eq_sc0 = ar[0] == sc[0];
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wire set_flags_et10 = et10 & (memac | ir_as);
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pa ar_pa0(); // AR+-1 T0
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pa ar_pa1(); // AR NEGATE T0
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@ -1125,6 +1128,8 @@ module apr(
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.p(ar_cry_comp_D));
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wire [0:35] ar_mb_cry = mb & ~ar;
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// hold the cry out temporarily
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reg cry0, cry1;
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always @(posedge clk) begin: arctl
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integer i;
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@ -1132,8 +1137,10 @@ module apr(
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ar[0:17] <= 0;
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if(arrt_clr)
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ar[18:35] <= 0;
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if(ar_cry_initiate)
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ar <= ar + { ar_mb_cry[1:35], 1'b0 };
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if(ar_cry_initiate) begin
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cry1 <= (ar[1:35] + { ar_mb_cry[2:35], 1'b0 }) + 36'o0 >> 35;
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{cry0, ar} <= ar + { ar_mb_cry[1:35], 1'b0 };
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end
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if(arlt_fm_mb_xor)
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ar[0:17] <= ar[0:17] ^ mb[0:17];
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if(arrt_fm_mb_xor)
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@ -1161,6 +1168,48 @@ module apr(
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ar_cry0_flag <= 0;
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ar_cry1_flag <= 0;
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end
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if(ar_jfcl_clr & ir[12] |
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cpa_cono_set & iob[29])
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ar_pc_chg_flag <= 0;
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if(ar_flag_set & mb[3] |
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et9 & pc_set_OR_pc_inc & ~ar_jrst_AND_ir11)
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ar_pc_chg_flag <= 1;
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if(ar_jfcl_clr & ir[9] |
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cpa_cono_set & iob[32])
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ar_ov_flag <= 0;
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if(ar_flag_set & mb[0] |
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set_flags_et10 & ar_ov_set |
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cfac_overflow |
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et10 & ir_fwt & ~ar_cry0 & ar_cry1 |
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sct1 & ~mb[18] & ir_ash_OR_ashc | ar0_xor_ar1)
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ar_ov_flag <= 1;
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if(ar_jfcl_clr & ir[10])
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ar_cry0_flag <= 0;
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if(ar_flag_set & mb[1] |
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set_flags_et10 & ar_cry0)
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ar_cry0_flag <= 1;
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if(ar_jfcl_clr & ir[11])
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ar_cry1_flag <= 0;
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if(ar_flag_set & mb[2] |
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set_flags_et10 & ar_cry1)
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ar_cry1_flag <= 1;
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if(mr_start) begin
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cry0 <= 0;
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cry1 <= 0;
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end
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if(cry0) begin
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cry0 <= 0;
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ar_cry0 <= 1;
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end
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if(cry1) begin
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cry1 <= 0;
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ar_cry1 <= 1;
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end
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if(et0) begin
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ar_cry0 <= 0;
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ar_cry1 <= 0;
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@ -1839,6 +1888,7 @@ module apr(
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assign iobus_iob_fm_datai = 0;
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assign iobus_iob_fm_status = 0;
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assign iobus_iob_out = 0;
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wire [0:35] iob = iobus_iob_in;
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/*
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* PIH, PIR, PIO
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@ -22,9 +22,13 @@ module test;
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clock clock0(clk);
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pdp6 pdp6(.clk(clk), .reset(reset));
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initial
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initial begin
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// #110000 $finish;
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#20000 $finish;
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end
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always @(pdp6.apr0.st7)
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if(pdp6.apr0.st7)
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$finish;
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initial begin
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#100 `TESTKEY = 1;
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@ -117,15 +121,15 @@ module test;
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pdp6.datasw = 36'o111777222666;
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// pdp6.mas = 18'o010100;
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// pdp6.mas = 18'o000004;
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pdp6.mas = 18'o000020;
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pdp6.mas = 18'o000023;
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//pdp6.mas = 18'o777777;
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pdp6.fmem0.ff['o0] = 36'o000000010000;
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pdp6.fmem0.ff['o1] = 36'o000000000222;
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pdp6.fmem0.ff['o2] = 36'o700000000006;
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pdp6.fmem0.ff['o3] = 36'o500000000004;
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pdp6.fmem0.ff['o4] = 36'o000000010304;
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pdp6.mem0.core['o4] = 36'o222333111666;
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pdp6.fmem0.ff['o0] = 36'o000000_010000;
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pdp6.fmem0.ff['o1] = 36'o000000_000222;
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pdp6.fmem0.ff['o2] = 36'o700000_000006;
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pdp6.fmem0.ff['o3] = 36'o500000_000004;
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pdp6.fmem0.ff['o4] = 36'o000000_010304;
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pdp6.fmem0.ff['o5] = 36'o377777_777777;
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// MOVE 1,@104(4) FAC_INH
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pdp6.mem0.core['o20] = 36'o200_064_000104;
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// MOVEM 1,@104(4)
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@ -133,6 +137,8 @@ module test;
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// ROTC 2,3
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pdp6.mem0.core['o22] = 36'o245_100_000003;
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pdp6.mem0.core['o23] = 36'o200_005_000001;
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pdp6.mem0.core['o10410] = 36'o000_000_000333;
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end
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