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verilog: passing diag part 3
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aap
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@ -431,6 +431,7 @@ X typestr("<SETPC>\r\n");
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cpu_stopinst();
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X run = 0;
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// TODO: maybe INSTSTOP?
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keydown(MM6_MEMSTOP);
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keyup(MM6_ADRSTOP);
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set_ta(a);
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@ -495,6 +496,7 @@ X typestr("<CONT>\r\n");
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// on stop the machine should halt after one instruction
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// so restart
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// BUG: if next instruction is HALT we'll continue past it
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if(stop){
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waithalt();
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togglecont();
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@ -977,45 +977,52 @@ module apr(
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wire mbrt_fm_mbltJ = mblt_mbrt_swap;
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wire mb_fm_pc1 = mb_fm_pc1_init;
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// ET0
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wire mb_fm_mqJ_et0 = jp_pop | jp_popj | jp_jra;
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wire mb_ar_swap_et0 = hwt_10 | jp_jsp | ir_exch | ir_blt | ir_fsb;
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wire mb_fm_arJ_et0 = fwt_01 | fwt_10 | iot_status;
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wire mbltrtJ_et0 = acbm_swap | iot_cono | jp_jsa;
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// ET1
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wire mb_fm_ar0_et1 = ir_acbm;
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wire mbltrtJ_et1 = hwt_swap | fwt_swap | ir_blt;
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// ET4
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wire mb_ar_swap_et4 = fwt_swap | iot_blk | ir_acbm;
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// ET6
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wire mb_fm_pc1_et6 = jp_jsa;
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// ET9
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wire mb_ar_swap_et9 = ir_acbm | jp_AND_NOT_jsr;
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// ET10
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wire mb_fm_arJ_inh_et10 = ir_jp | ir_exch | ch_dep;
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wire mb_ar_swap_et10 = jp_AND_ir6_0;
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wire mb_fm_arJ_et10 = (f_c_e_pse | s_c_e) & ~mb_fm_arJ_inh_et10;
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wire mb_clr = et5 & mb_pc_sto |
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mc_mb_clr_D;
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wire mblt_mbrt_swap = et0a & mbltrtJ_et0 |
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et1 & mbltrtJ_et1 |
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ft1a & f_c_c_aclt;
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wire mbltrtJ_et0 = acbm_swap | iot_cono | jp_jsa;
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wire mbltrtJ_et1 = hwt_swap | fwt_swap | ir_blt;
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wire mb_fm_misc_bits1 = et6 & jp_flag_stor;
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wire mb_fm_ar0 = et1 & mb_fm_ar0_et1 |
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dct3 |
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et6 & acbm_cl;
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wire mb_fm_ar0_et1 = ir_acbm;
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wire mb_fm_arJ = at3a | st5 | key_wr | dst1 | mst1 |
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et0a & mb_fm_arJ_et0 |
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et10 & mb_fm_arJ_et10 |
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kt3 & key_execute;
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wire mb_fm_arJ_et0 = fwt_01 | fwt_10 | iot_status;
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wire mb_fm_arJ_et10 = (f_c_e_pse | s_c_e) & ~mb_fm_arJ_inh_et10;
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wire mb_fm_arJ_inh_et10 = ir_jp | ir_exch | ch_dep;
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wire mb_ar_swap = ft3 | blt_t1 | blt_t4 | blt_t6 |
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et0a & mb_ar_swap_et0 |
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et4 & mb_ar_swap_et4 |
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et9 & mb_ar_swap_et9 |
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et10 & mb_ar_swap_et10 |
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ft1a & ~f_c_c_aclt_OR_rt;
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wire mb_ar_swap_et0 = hwt_10 | jp_jsp | ir_exch | ir_blt | ir_fsb;
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wire mb_ar_swap_et4 = fwt_swap | iot_blk | ir_acbm;
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wire mb_ar_swap_et9 = ir_acbm | jp_AND_NOT_jsr;
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wire mb_ar_swap_et10 = jp_AND_ir6_0;
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wire mb_fm_mqJ = st6 | ft4a | blt_t0a |
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et0a & mb_fm_mqJ_et0;
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wire mb_fm_mqJ_et0 = jp_pop | jp_popj | jp_jra;
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wire mb1_8_clr = (fpt3 | fat8a) & ~mb[0];
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wire mb1_8_set = (fpt3 | fat8a) & mb[0];
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wire mblt_fm_ir1_uuo_t0 = et3 & ex_ir_uuo;
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wire mb_fm_pc1_init = et6 & mb_pc_sto |
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et6 & mb_fm_pc1_et6;
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wire mb_pc_sto = jp_pushj | jp_jsr | jp_jsp | ir_jrst;
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wire mb_fm_pc1_et6 = jp_jsa;
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wire mc_mb_clr_D;
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dly100ns mb_dly0(.clk(clk), .reset(rst), .in(mc_mb_clr), .p(mc_mb_clr_D));
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@ -1056,7 +1063,7 @@ module apr(
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if(mb_fm_pc1)
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mb[18:35] <= mb[18:35] | pc;
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if(mb_fm_ir1)
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mb[18:35] <= mb[18:35] | ir;
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mb[0:17] <= mb[0:17] | { ir[0:12], 5'b0 };
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if(mb1_8_clr)
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mb[1:8] <= 0;
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if(mb1_8_set)
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@ -2056,7 +2063,8 @@ module apr(
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.in((fat3_D | fat4_D) & sc0_2_eq_7),
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.p(fat5));
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pa fa_pa8(.clk(clk), .reset(rst),
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.in(sct2 & faf3),
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.in(sct2 & faf3 |
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fat6),
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.p(fat5a));
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pa fa_pa9(.clk(clk), .reset(rst),
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.in((fat3_D | fat4_D) & ~sc0_2_eq_7),
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@ -2732,13 +2740,13 @@ module apr(
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assign maN_set[30] = ma_fm_pich |
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et3 & ex_ir_uuo;
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assign maN_set[31] = 0;
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assign maN_set[32] = pi_enc_32 |
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assign maN_set[32] = ma_fm_pich & pi_enc_32 |
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ma_fm_ir14_17 & ir[14] |
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ma_fm_ir9_12 & ir[9];
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assign maN_set[33] = pi_enc_33 |
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assign maN_set[33] = ma_fm_pich & pi_enc_33 |
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ma_fm_ir14_17 & ir[15] |
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ma_fm_ir9_12 & ir[10];
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assign maN_set[34] = pi_enc_34 |
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assign maN_set[34] = ma_fm_pich & pi_enc_34 |
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ma_fm_ir14_17 & ir[16] |
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ma_fm_ir9_12 & ir[11];
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assign maN_set[35] =
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@ -3153,6 +3161,7 @@ module apr(
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pir[i] <= 1;
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end
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else
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if(pih) // HACK so it can be set from testbench
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pir <= pir & ~pih;
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if(pi_reset)
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@ -144,7 +144,6 @@ module core161c_x(
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wire cmc_strb_sa;
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wire cmc_proc_rs_P;
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wire mb_pulse_out;
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wire mb_pulse_in;
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wire cmc_wr_rs;
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wire cmc_t0;
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wire cmc_t1;
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@ -149,7 +149,7 @@ module fast162(
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.p(fmc_restart));
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pg fmc_pg2(.clk(clk), .reset(reset), .in(fmc_act), .p(fmct0));
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pg fmc_pg3(.clk(clk), .reset(reset), .in(fma_rd_rq), .p(fma_rd_rq_P));
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pg cmc_pg5(.clk(clk), .reset(reset), .in(wr_rs), .p(fmc_wr_rs));
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pg fmc_pg5(.clk(clk), .reset(reset), .in(wr_rs), .p(fmc_wr_rs));
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pa fmc_pa0(.clk(clk), .reset(reset),
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.in(fmc_start |
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@ -167,7 +167,7 @@ module fast162(
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pa fmc_pa4(.clk(clk), .reset(reset),
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.in(fmct3_D),
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.p(fmc_wr_set));
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pg fmc_pg5(.clk(clk), .reset(reset),
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pg fmc_pa5(.clk(clk), .reset(reset),
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.in(fmct0 & ~fma_rd_rq & fma_wr_rq |
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fmct1_D & fma_wr_rq),
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.p(fmct3));
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@ -116,7 +116,7 @@ module bd(input clk, input reset, input in, output p);
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r <= 1;
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end
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end
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assign p = r == 4;
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assign p = r == 2;
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endmodule
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/* Same as above but with longer pulse. Used to pulse mb
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@ -135,5 +135,5 @@ module bd2(input clk, input reset, input in, output p);
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r <= 1;
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end
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end
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assign p = r == 4 || r == 5 || r == 6 || r == 7;
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assign p = r == 2 || r == 3 || r == 4 || r == 5;
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endmodule
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@ -209,31 +209,51 @@ module tb_apr();
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.membus_mb_in_p3(36'b0)
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);
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initial begin
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initial begin: init
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integer i;
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$dumpfile("dump.vcd");
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$dumpvars();
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cmem.core['o1323] <= 36'o215000000001;
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cmem.core['o1324] <= 36'o254200000000;
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for(i = 0; i < 'o40000; i = i + 1)
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cmem.core[i] <= 0;
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cmem.core['o100] <= 36'o200000000105;
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cmem.core['o101] <= 36'o202000000041;
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cmem.core['o102] <= 36'o254200000000;
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#10;
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cmem.core['o105] <= 36'o000000001234;
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cmem.core['o42] <= 36'o334000_000000;
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cmem.core['o43] <= 36'o000000_000000;
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cmem.core['o44] <= 36'o334000_000000;
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cmem.core['o45] <= 36'o000000_000000;
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cmem.core['o46] <= 36'o334000_000000;
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cmem.core['o47] <= 36'o000000_000000;
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cmem.core['o50] <= 36'o334000_000000;
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cmem.core['o51] <= 36'o000000_000000;
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cmem.core['o52] <= 36'o334000_000000;
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cmem.core['o53] <= 36'o000000_000000;
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// fmem.ff[0] <= 36'o1;
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mas <= 'o100;
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cmem.core['o1733] <= 36'o300000_000000;
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cmem.core['o1734] <= 36'o254400001736; // jrst 10,1736
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cmem.core['o1735] <= 36'o254200000000;
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cmem.core['o1736] <= 36'o254200000001;
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cmem.core['o1737] <= 36'o254200000002;
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fmem.ff[0] <= 36'o0;
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fmem.ff[1] <= 36'o0;
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mas <= 'o1733;
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#200;
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sw_power <= 1;
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#200;
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key_mem_stop <= 1;
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// key_mem_stop <= 1;
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apr.pir <= 'o177;
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apr.pi_active <= 1;
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key_start <= 1;
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#1000;
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key_start <= 0;
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/*
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#500;
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key_mem_stop <= 0;
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@ -246,7 +266,7 @@ module tb_apr();
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key_inst_cont <= 1;
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#500;
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key_inst_cont <= 0;
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*/
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end
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initial begin
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@ -136,7 +136,6 @@ module core161c(
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wire cmc_strb_sa;
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wire cmc_proc_rs_P;
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wire mb_pulse_out;
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wire mb_pulse_in;
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wire cmc_wr_rs;
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wire cmc_t0;
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wire cmc_t1;
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@ -160,7 +159,6 @@ module core161c(
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pg cmc_pg2(.clk(clk), .reset(reset),
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.in(cmpc_p0_rq | cmpc_p1_rq | cmpc_p2_rq | cmpc_p3_rq),
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.p(cmc_t0));
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pg cmc_pg3(.clk(clk), .reset(reset), .in(| mb_in), .p(mb_pulse_in));
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pg cmc_pg4(.clk(clk), .reset(reset), .in(wr_rs), .p(cmpc_rs_strb));
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pg cmc_pg5(.clk(clk), .reset(reset), .in(cmc_proc_rs), .p(cmc_proc_rs_P));
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pg cmc_pg6(.clk(clk), .reset(reset), .in(cmc_pse_sync & cmc_proc_rs), .p(cmc_wr_rs));
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@ -194,9 +192,9 @@ module core161c(
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.p(cmc_strb_sa));
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// not on schematics
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bd cmc_bd0(.clk(clk), .reset(reset), .in(cmc_t1), .p(cmc_addr_ack));
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bd cmc_bd1(.clk(clk), .reset(reset), .in(cmc_strb_sa_D0), .p(cmc_rd_rs));
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bd2 cmc_bd2(.clk(clk), .reset(reset), .in(cmc_strb_sa), .p(mb_pulse_out));
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bd cmc_bd0(.clk(clk), .reset(reset), .in(cmc_t1), .p(cmc_addr_ack));
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bd cmc_bd1(.clk(clk), .reset(reset), .in(cmc_strb_sa_D0), .p(cmc_rd_rs));
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bd cmc_bd2(.clk(clk), .reset(reset), .in(cmc_strb_sa), .p(mb_pulse_out));
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wire cmc_pwr_clr_D;
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wire cmc_t0_D, cmc_t1_D, cmc_t2_D0, cmc_t2_D1, cmc_t4_D;
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@ -252,14 +250,14 @@ module core161c(
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cmc_p2_act <= 0;
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cmc_p3_act <= 0;
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end
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cmb <= cmb | mb_in;
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if(cmc_cmb_clr)
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cmb <= 0;
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if(cmc_strb_sa)
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cmb <= cmb | sa;
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if(mb_pulse_in)
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cmb <= cmb | mb_in;
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if(cmpc_rs_strb)
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cmc_proc_rs <= 1;
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if(cmc_t0) begin
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cmc_await_rq <= 0;
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cmc_proc_rs <= 0;
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