github.com/aap.pdp6
1
0
Fork 0
mirror of https://github.com/aap/pdp6.git synced 2026-05-03 14:48:44 +00:00
Code Issues Releases Wiki Activity

verilog: passing diag part 3

Browse Source
This commit is contained in:
aap
2019-10-29 14:13:52 +01:00
parent b96e2d468d
commit a8b07f4340
7 changed files with 68 additions and 40 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
fe6/real6.c
View File

@@ -431,6 +431,7 @@ X typestr("<SETPC>\r\n");
cpu_stopinst(); cpu_stopinst();
X run = 0; X run = 0;
// TODO: maybe INSTSTOP?
keydown(MM6_MEMSTOP); keydown(MM6_MEMSTOP);
keyup(MM6_ADRSTOP); keyup(MM6_ADRSTOP);
set_ta(a); set_ta(a);
@@ -495,6 +496,7 @@ X typestr("<CONT>\r\n");
// on stop the machine should halt after one instruction // on stop the machine should halt after one instruction
// so restart // so restart
// BUG: if next instruction is HALT we'll continue past it
if(stop){ if(stop){
waithalt(); waithalt();
togglecont(); togglecont();

43
verilog/apr.v
View File

@@ -977,45 +977,52 @@ module apr(
wire mbrt_fm_mbltJ = mblt_mbrt_swap; wire mbrt_fm_mbltJ = mblt_mbrt_swap;
wire mb_fm_pc1 = mb_fm_pc1_init; wire mb_fm_pc1 = mb_fm_pc1_init;
// ET0
wire mb_fm_mqJ_et0 = jp_pop | jp_popj | jp_jra;
wire mb_ar_swap_et0 = hwt_10 | jp_jsp | ir_exch | ir_blt | ir_fsb;
wire mb_fm_arJ_et0 = fwt_01 | fwt_10 | iot_status;
wire mbltrtJ_et0 = acbm_swap | iot_cono | jp_jsa;
// ET1
wire mb_fm_ar0_et1 = ir_acbm;
wire mbltrtJ_et1 = hwt_swap | fwt_swap | ir_blt;
// ET4
wire mb_ar_swap_et4 = fwt_swap | iot_blk | ir_acbm;
// ET6
wire mb_fm_pc1_et6 = jp_jsa;
// ET9
wire mb_ar_swap_et9 = ir_acbm | jp_AND_NOT_jsr;
// ET10
wire mb_fm_arJ_inh_et10 = ir_jp | ir_exch | ch_dep;
wire mb_ar_swap_et10 = jp_AND_ir6_0;
wire mb_fm_arJ_et10 = (f_c_e_pse | s_c_e) & ~mb_fm_arJ_inh_et10;
wire mb_clr = et5 & mb_pc_sto | wire mb_clr = et5 & mb_pc_sto |
mc_mb_clr_D; mc_mb_clr_D;
wire mblt_mbrt_swap = et0a & mbltrtJ_et0 | wire mblt_mbrt_swap = et0a & mbltrtJ_et0 |
et1 & mbltrtJ_et1 | et1 & mbltrtJ_et1 |
ft1a & f_c_c_aclt; ft1a & f_c_c_aclt;
wire mbltrtJ_et0 = acbm_swap | iot_cono | jp_jsa;
wire mbltrtJ_et1 = hwt_swap | fwt_swap | ir_blt;
wire mb_fm_misc_bits1 = et6 & jp_flag_stor; wire mb_fm_misc_bits1 = et6 & jp_flag_stor;
wire mb_fm_ar0 = et1 & mb_fm_ar0_et1 | wire mb_fm_ar0 = et1 & mb_fm_ar0_et1 |
dct3 | dct3 |
et6 & acbm_cl; et6 & acbm_cl;
wire mb_fm_ar0_et1 = ir_acbm;
wire mb_fm_arJ = at3a | st5 | key_wr | dst1 | mst1 | wire mb_fm_arJ = at3a | st5 | key_wr | dst1 | mst1 |
et0a & mb_fm_arJ_et0 | et0a & mb_fm_arJ_et0 |
et10 & mb_fm_arJ_et10 | et10 & mb_fm_arJ_et10 |
kt3 & key_execute; kt3 & key_execute;
wire mb_fm_arJ_et0 = fwt_01 | fwt_10 | iot_status;
wire mb_fm_arJ_et10 = (f_c_e_pse | s_c_e) & ~mb_fm_arJ_inh_et10;
wire mb_fm_arJ_inh_et10 = ir_jp | ir_exch | ch_dep;
wire mb_ar_swap = ft3 | blt_t1 | blt_t4 | blt_t6 | wire mb_ar_swap = ft3 | blt_t1 | blt_t4 | blt_t6 |
et0a & mb_ar_swap_et0 | et0a & mb_ar_swap_et0 |
et4 & mb_ar_swap_et4 | et4 & mb_ar_swap_et4 |
et9 & mb_ar_swap_et9 | et9 & mb_ar_swap_et9 |
et10 & mb_ar_swap_et10 | et10 & mb_ar_swap_et10 |
ft1a & ~f_c_c_aclt_OR_rt; ft1a & ~f_c_c_aclt_OR_rt;
wire mb_ar_swap_et0 = hwt_10 | jp_jsp | ir_exch | ir_blt | ir_fsb;
wire mb_ar_swap_et4 = fwt_swap | iot_blk | ir_acbm;
wire mb_ar_swap_et9 = ir_acbm | jp_AND_NOT_jsr;
wire mb_ar_swap_et10 = jp_AND_ir6_0;
wire mb_fm_mqJ = st6 | ft4a | blt_t0a | wire mb_fm_mqJ = st6 | ft4a | blt_t0a |
et0a & mb_fm_mqJ_et0; et0a & mb_fm_mqJ_et0;
wire mb_fm_mqJ_et0 = jp_pop | jp_popj | jp_jra;
wire mb1_8_clr = (fpt3 | fat8a) & ~mb[0]; wire mb1_8_clr = (fpt3 | fat8a) & ~mb[0];
wire mb1_8_set = (fpt3 | fat8a) & mb[0]; wire mb1_8_set = (fpt3 | fat8a) & mb[0];
wire mblt_fm_ir1_uuo_t0 = et3 & ex_ir_uuo; wire mblt_fm_ir1_uuo_t0 = et3 & ex_ir_uuo;
wire mb_fm_pc1_init = et6 & mb_pc_sto | wire mb_fm_pc1_init = et6 & mb_pc_sto |
et6 & mb_fm_pc1_et6; et6 & mb_fm_pc1_et6;
wire mb_pc_sto = jp_pushj | jp_jsr | jp_jsp | ir_jrst; wire mb_pc_sto = jp_pushj | jp_jsr | jp_jsp | ir_jrst;
wire mb_fm_pc1_et6 = jp_jsa;
wire mc_mb_clr_D; wire mc_mb_clr_D;
dly100ns mb_dly0(.clk(clk), .reset(rst), .in(mc_mb_clr), .p(mc_mb_clr_D)); dly100ns mb_dly0(.clk(clk), .reset(rst), .in(mc_mb_clr), .p(mc_mb_clr_D));
@@ -1056,7 +1063,7 @@ module apr(
if(mb_fm_pc1) if(mb_fm_pc1)
mb[18:35] <= mb[18:35] | pc; mb[18:35] <= mb[18:35] | pc;
if(mb_fm_ir1) if(mb_fm_ir1)
mb[18:35] <= mb[18:35] | ir; mb[0:17] <= mb[0:17] | { ir[0:12], 5'b0 };
if(mb1_8_clr) if(mb1_8_clr)
mb[1:8] <= 0; mb[1:8] <= 0;
if(mb1_8_set) if(mb1_8_set)
@@ -2056,7 +2063,8 @@ module apr(
.in((fat3_D | fat4_D) & sc0_2_eq_7), .in((fat3_D | fat4_D) & sc0_2_eq_7),
.p(fat5)); .p(fat5));
pa fa_pa8(.clk(clk), .reset(rst), pa fa_pa8(.clk(clk), .reset(rst),
.in(sct2 & faf3), .in(sct2 & faf3 |
fat6),
.p(fat5a)); .p(fat5a));
pa fa_pa9(.clk(clk), .reset(rst), pa fa_pa9(.clk(clk), .reset(rst),
.in((fat3_D | fat4_D) & ~sc0_2_eq_7), .in((fat3_D | fat4_D) & ~sc0_2_eq_7),
@@ -2732,13 +2740,13 @@ module apr(
assign maN_set[30] = ma_fm_pich | assign maN_set[30] = ma_fm_pich |
et3 & ex_ir_uuo; et3 & ex_ir_uuo;
assign maN_set[31] = 0; assign maN_set[31] = 0;
assign maN_set[32] = pi_enc_32 | assign maN_set[32] = ma_fm_pich & pi_enc_32 |
ma_fm_ir14_17 & ir[14] | ma_fm_ir14_17 & ir[14] |
ma_fm_ir9_12 & ir[9]; ma_fm_ir9_12 & ir[9];
assign maN_set[33] = pi_enc_33 | assign maN_set[33] = ma_fm_pich & pi_enc_33 |
ma_fm_ir14_17 & ir[15] | ma_fm_ir14_17 & ir[15] |
ma_fm_ir9_12 & ir[10]; ma_fm_ir9_12 & ir[10];
assign maN_set[34] = pi_enc_34 | assign maN_set[34] = ma_fm_pich & pi_enc_34 |
ma_fm_ir14_17 & ir[16] | ma_fm_ir14_17 & ir[16] |
ma_fm_ir9_12 & ir[11]; ma_fm_ir9_12 & ir[11];
assign maN_set[35] = assign maN_set[35] =
@@ -3153,6 +3161,7 @@ module apr(
pir[i] <= 1; pir[i] <= 1;
end end
else else
if(pih) // HACK so it can be set from testbench
pir <= pir & ~pih; pir <= pir & ~pih;
if(pi_reset) if(pi_reset)

1
verilog/core161c.v
View File

@@ -144,7 +144,6 @@ module core161c_x(
wire cmc_strb_sa; wire cmc_strb_sa;
wire cmc_proc_rs_P; wire cmc_proc_rs_P;
wire mb_pulse_out; wire mb_pulse_out;
wire mb_pulse_in;
wire cmc_wr_rs; wire cmc_wr_rs;
wire cmc_t0; wire cmc_t0;
wire cmc_t1; wire cmc_t1;

4
verilog/fast162.v
View File

@@ -149,7 +149,7 @@ module fast162(
.p(fmc_restart)); .p(fmc_restart));
pg fmc_pg2(.clk(clk), .reset(reset), .in(fmc_act), .p(fmct0)); pg fmc_pg2(.clk(clk), .reset(reset), .in(fmc_act), .p(fmct0));
pg fmc_pg3(.clk(clk), .reset(reset), .in(fma_rd_rq), .p(fma_rd_rq_P)); pg fmc_pg3(.clk(clk), .reset(reset), .in(fma_rd_rq), .p(fma_rd_rq_P));
pg cmc_pg5(.clk(clk), .reset(reset), .in(wr_rs), .p(fmc_wr_rs)); pg fmc_pg5(.clk(clk), .reset(reset), .in(wr_rs), .p(fmc_wr_rs));
pa fmc_pa0(.clk(clk), .reset(reset), pa fmc_pa0(.clk(clk), .reset(reset),
.in(fmc_start | .in(fmc_start |
@@ -167,7 +167,7 @@ module fast162(
pa fmc_pa4(.clk(clk), .reset(reset), pa fmc_pa4(.clk(clk), .reset(reset),
.in(fmct3_D), .in(fmct3_D),
.p(fmc_wr_set)); .p(fmc_wr_set));
pg fmc_pg5(.clk(clk), .reset(reset), pg fmc_pa5(.clk(clk), .reset(reset),
.in(fmct0 & ~fma_rd_rq & fma_wr_rq | .in(fmct0 & ~fma_rd_rq & fma_wr_rq |
fmct1_D & fma_wr_rq), fmct1_D & fma_wr_rq),
.p(fmct3)); .p(fmct3));

4
verilog/modules_50.v
View File

@@ -116,7 +116,7 @@ module bd(input clk, input reset, input in, output p);
r <= 1; r <= 1;
end end
end end
assign p = r == 4; assign p = r == 2;
endmodule endmodule
/* Same as above but with longer pulse. Used to pulse mb /* Same as above but with longer pulse. Used to pulse mb
@@ -135,5 +135,5 @@ module bd2(input clk, input reset, input in, output p);
r <= 1; r <= 1;
end end
end end
assign p = r == 4 || r == 5 || r == 6 || r == 7; assign p = r == 2 || r == 3 || r == 4 || r == 5;
endmodule endmodule

42
verilog/tb/tb_apr.v
View File

@@ -209,31 +209,51 @@ module tb_apr();
.membus_mb_in_p3(36'b0) .membus_mb_in_p3(36'b0)
); );
initial begin initial begin: init
integer i;
$dumpfile("dump.vcd"); $dumpfile("dump.vcd");
$dumpvars(); $dumpvars();
cmem.core['o1323] <= 36'o215000000001; for(i = 0; i < 'o40000; i = i + 1)
cmem.core['o1324] <= 36'o254200000000; cmem.core[i] <= 0;
cmem.core['o100] <= 36'o200000000105; #10;
cmem.core['o101] <= 36'o202000000041;
cmem.core['o102] <= 36'o254200000000;
cmem.core['o105] <= 36'o000000001234; cmem.core['o42] <= 36'o334000_000000;
cmem.core['o43] <= 36'o000000_000000;
cmem.core['o44] <= 36'o334000_000000;
cmem.core['o45] <= 36'o000000_000000;
cmem.core['o46] <= 36'o334000_000000;
cmem.core['o47] <= 36'o000000_000000;
cmem.core['o50] <= 36'o334000_000000;
cmem.core['o51] <= 36'o000000_000000;
cmem.core['o52] <= 36'o334000_000000;
cmem.core['o53] <= 36'o000000_000000;
// fmem.ff[0] <= 36'o1; cmem.core['o1733] <= 36'o300000_000000;
mas <= 'o100; cmem.core['o1734] <= 36'o254400001736; // jrst 10,1736
cmem.core['o1735] <= 36'o254200000000;
cmem.core['o1736] <= 36'o254200000001;
cmem.core['o1737] <= 36'o254200000002;
fmem.ff[0] <= 36'o0;
fmem.ff[1] <= 36'o0;
mas <= 'o1733;
#200; #200;
sw_power <= 1; sw_power <= 1;
#200; #200;
key_mem_stop <= 1; // key_mem_stop <= 1;
apr.pir <= 'o177;
apr.pi_active <= 1;
key_start <= 1; key_start <= 1;
#1000; #1000;
key_start <= 0; key_start <= 0;
/*
#500; #500;
key_mem_stop <= 0; key_mem_stop <= 0;
@@ -246,7 +266,7 @@ module tb_apr();
key_inst_cont <= 1; key_inst_cont <= 1;
#500; #500;
key_inst_cont <= 0; key_inst_cont <= 0;
*/
end end
initial begin initial begin

12
verilog/testcore161c.v
View File

@@ -136,7 +136,6 @@ module core161c(
wire cmc_strb_sa; wire cmc_strb_sa;
wire cmc_proc_rs_P; wire cmc_proc_rs_P;
wire mb_pulse_out; wire mb_pulse_out;
wire mb_pulse_in;
wire cmc_wr_rs; wire cmc_wr_rs;
wire cmc_t0; wire cmc_t0;
wire cmc_t1; wire cmc_t1;
@@ -160,7 +159,6 @@ module core161c(
pg cmc_pg2(.clk(clk), .reset(reset), pg cmc_pg2(.clk(clk), .reset(reset),
.in(cmpc_p0_rq | cmpc_p1_rq | cmpc_p2_rq | cmpc_p3_rq), .in(cmpc_p0_rq | cmpc_p1_rq | cmpc_p2_rq | cmpc_p3_rq),
.p(cmc_t0)); .p(cmc_t0));
pg cmc_pg3(.clk(clk), .reset(reset), .in(| mb_in), .p(mb_pulse_in));
pg cmc_pg4(.clk(clk), .reset(reset), .in(wr_rs), .p(cmpc_rs_strb)); pg cmc_pg4(.clk(clk), .reset(reset), .in(wr_rs), .p(cmpc_rs_strb));
pg cmc_pg5(.clk(clk), .reset(reset), .in(cmc_proc_rs), .p(cmc_proc_rs_P)); pg cmc_pg5(.clk(clk), .reset(reset), .in(cmc_proc_rs), .p(cmc_proc_rs_P));
pg cmc_pg6(.clk(clk), .reset(reset), .in(cmc_pse_sync & cmc_proc_rs), .p(cmc_wr_rs)); pg cmc_pg6(.clk(clk), .reset(reset), .in(cmc_pse_sync & cmc_proc_rs), .p(cmc_wr_rs));
@@ -194,9 +192,9 @@ module core161c(
.p(cmc_strb_sa)); .p(cmc_strb_sa));
// not on schematics // not on schematics
bd cmc_bd0(.clk(clk), .reset(reset), .in(cmc_t1), .p(cmc_addr_ack)); bd cmc_bd0(.clk(clk), .reset(reset), .in(cmc_t1), .p(cmc_addr_ack));
bd cmc_bd1(.clk(clk), .reset(reset), .in(cmc_strb_sa_D0), .p(cmc_rd_rs)); bd cmc_bd1(.clk(clk), .reset(reset), .in(cmc_strb_sa_D0), .p(cmc_rd_rs));
bd2 cmc_bd2(.clk(clk), .reset(reset), .in(cmc_strb_sa), .p(mb_pulse_out)); bd cmc_bd2(.clk(clk), .reset(reset), .in(cmc_strb_sa), .p(mb_pulse_out));
wire cmc_pwr_clr_D; wire cmc_pwr_clr_D;
wire cmc_t0_D, cmc_t1_D, cmc_t2_D0, cmc_t2_D1, cmc_t4_D; wire cmc_t0_D, cmc_t1_D, cmc_t2_D0, cmc_t2_D1, cmc_t4_D;
@@ -252,14 +250,14 @@ module core161c(
cmc_p2_act <= 0; cmc_p2_act <= 0;
cmc_p3_act <= 0; cmc_p3_act <= 0;
end end
cmb <= cmb | mb_in;
if(cmc_cmb_clr) if(cmc_cmb_clr)
cmb <= 0; cmb <= 0;
if(cmc_strb_sa) if(cmc_strb_sa)
cmb <= cmb | sa; cmb <= cmb | sa;
if(mb_pulse_in)
cmb <= cmb | mb_in;
if(cmpc_rs_strb) if(cmpc_rs_strb)
cmc_proc_rs <= 1; cmc_proc_rs <= 1;
if(cmc_t0) begin if(cmc_t0) begin
cmc_await_rq <= 0; cmc_await_rq <= 0;
cmc_proc_rs <= 0; cmc_proc_rs <= 0;