fixed emu; new verilog code; fe6 for fpga

verilog/fe_req.v

@@ -0,0 +1,13 @@
+module fe_req(
+	// unused
+	input wire clk,
+	input wire reset,
+
+	// requests
+	input wire [31:0] req,
+
+	// Avalon slave
+	output wire [31:0] readdata
+);
+	assign readdata = req;
+endmodule