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verilog instruction decoding
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@@ -1,5 +1,8 @@
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a.out: test.v pdp6.v apr.v core161c.v fast162.v modules.v
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iverilog test.v pdp6.v apr.v core161c.v fast162.v modules.v
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test: test.v pdp6.v apr.v core161c.v fast162.v modules.v
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iverilog -o test test.v pdp6.v apr.v core161c.v fast162.v modules.v
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run: a.out
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vvp a.out
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test_dec: test_dec.v pdp6.v apr.v core161c.v fast162.v modules.v
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iverilog -o test_dec test_dec.v pdp6.v apr.v core161c.v fast162.v modules.v
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run: test
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vvp test
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