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https://github.com/aap/pdp6.git
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implemented I and A cycles in verilog
This commit is contained in:
aap
parent
14a82a7e61
commit
a2f609fe66
408
verilog/apr.v
408
verilog/apr.v
@ -130,7 +130,7 @@ module apr(
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wire key_ma_inc = kt1 & key_ex_OR_dep_nxt;
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wire key_ar_clr = kt1 & key_execute_OR_dp_OR_dp_nxt;
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wire key_ar_fm_datasw1 = kt2 & key_execute_OR_dp_OR_dp_nxt |
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0; // TODO: cpa & iob <- datai
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cpa & iobus_iob_fm_datai;
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wire key_rd = kt3 & key_ex_OR_ex_nxt;
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wire key_wr = kt3 & key_dp_OR_dp_nxt;
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@ -168,6 +168,9 @@ module apr(
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run <= 0;
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key_ex_st <= 0;
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key_dep_st <= 0;
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ar <= 0;
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mb <= 0;
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mq <= 0;
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end
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always @(posedge clk) begin
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@ -209,12 +212,48 @@ module apr(
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* I
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*/
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reg if1a;
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wire at1_inh = 0;
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wire ia_NOT_int = 0;
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wire iat0 = 0;
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wire it0 = 0;
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wire it1 = 0;
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wire it1a = 0;
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wire at1_inh;
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// equivalent: ia_inh = at1_inh | (pi_rq & ~pi_cyc)
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wire ia_NOT_int = ~at1_inh & (~pi_rq | pi_cyc);
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wire iat0;
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wire it0;
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wire it1;
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wire it1a;
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pa i_pa0(.clk(clk), .reset(reset),
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.in(key_go | (st7 & key_run_AND_NOT_ex_OR_dep)),
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.p(it0));
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pa i_pa1(.clk(clk), .reset(reset),
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.in(pi_sync_D & pi_rq & ~pi_cyc),
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.p(iat0));
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pa i_pa2(.clk(clk), .reset(reset),
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.in(iat0_D1 |
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pi_sync_D & if1a & ia_NOT_int),
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.p(it1));
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pa i_pa3(.clk(clk), .reset(reset),
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.in(mc_rs_t1 & if1a),
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.p(it1a));
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wire it0_D, iat0_D0, iat0_D1;
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ldly100us i_dly0(.clk(clk), .reset(reset),
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.in(run_clr),
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.l(at1_inh));
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dly50ns i_dly1(.clk(clk), .reset(reset),
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.in(it0),
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.p(it0_D));
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dly100ns i_dly2(.clk(clk), .reset(reset),
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.in(iat0),
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.p(iat0_D0));
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dly200ns i_dly23(.clk(clk), .reset(reset),
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.in(iat0),
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.p(iat0_D1));
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always @(posedge clk) begin
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if(mr_clr | it1a)
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if1a <= 0;
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if(it0_D | it1 | uuo_t2)
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if1a <= 1;
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end
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/*
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* A
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@ -222,13 +261,58 @@ module apr(
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reg af0;
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reg af3;
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reg af3a;
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wire at0 = 0;
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wire at1 = 0;
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wire at2 = 0;
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wire at3 = 0;
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wire at3a = 0;
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wire at4 = 0;
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wire at5 = 0;
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wire at0;
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wire at1;
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wire at2;
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wire at3;
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wire at3a;
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wire at4;
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wire at5;
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pa a_pa0(.clk(clk), .reset(reset),
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.in(it1a | cht9 | mc_rs_t1 & af0),
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.p(at0));
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pa a_pa1(.clk(clk), .reset(reset),
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.in(pi_sync_D & ~if1a & ia_NOT_int),
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.p(at1));
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pa a_pa2(.clk(clk), .reset(reset),
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.in(at1 & ~ir14_17_eq_0),
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.p(at2));
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pa a_pa3(.clk(clk), .reset(reset),
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.in(mc_rs_t1 & af3),
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.p(at3));
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pa a_pa4(.clk(clk), .reset(reset),
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.in(ar_t3 & af3a),
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.p(at3a));
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pa a_pa5(.clk(clk), .reset(reset),
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.in(at1 & ir14_17_eq_0 | at3a_D),
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.p(at4));
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pa a_pa6(.clk(clk), .reset(reset),
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.in(at4 & ir[13]),
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.p(at5));
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wire at3a_D, at5_D;
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dly100ns a_dly0(.clk(clk), .reset(reset),
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.in(at3a),
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.p(at3a_D));
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dly50ns a_dly1(.clk(clk), .reset(reset),
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.in(at5),
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.p(at5_D));
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always @(posedge clk) begin
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if(mr_clr | at0)
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af0 <= 0;
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if(at5)
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af0 <= 1;
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if(mr_clr | at3)
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af3 <= 0;
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if(at2)
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af3 <= 1;
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if(mr_clr | at3a)
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af3a <= 0;
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if(at3)
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af3a <= 1;
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end
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/*
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* F
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@ -236,7 +320,7 @@ module apr(
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reg f1a;
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reg f4a;
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reg f6a;
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wire ft0 = 0;
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wire ft0;
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wire ft1 = 0;
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wire ft1a = 0;
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wire ft3 = 0;
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@ -255,6 +339,10 @@ module apr(
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wire f_c_e_pse = 0;
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wire f_c_e_OR_pse = 0;
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pa f_pa0(.clk(clk), .reset(reset),
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.in(at4 & ~ir[13] | iot_t0a_D),
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.p(ft0));
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/*
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* E
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*/
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@ -298,10 +386,24 @@ module apr(
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* IR
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*/
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reg [0:17] ir;
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wire ir0_12_clr = 0;
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wire ir13_17_clr = 0;
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wire ir0_12_fm_mb1 = 0;
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wire ir13_17_fm_mb1 = 0;
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assign iobus_ios = ir[3:9];
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wire ir0_12_clr = mr_clr;
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wire ir13_17_clr = mr_clr | at5_D | cht8a;
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wire ir0_12_fm_mb1 = it1a;
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wire ir13_17_fm_mb1 = at0;
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always @(posedge clk) begin
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if(ir0_12_clr)
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ir[0:12] <= 0;
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if(ir13_17_clr)
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ir[13:17] <= 0;
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if(ir0_12_fm_mb1)
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ir[0:12] <= ir[0:12] | mb[0:12];
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if(ir13_17_fm_mb1)
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ir[13:17] <= ir[13:17] | mb[13:17];
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if(iot_t0a)
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ir[12] <= 1;
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end
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wire ir_uuo_a = 0;
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wire ir_fpch = 0;
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@ -369,7 +471,7 @@ module apr(
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wire ir_fsb = 0;
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wire ir_fmp = 0;
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wire ir_fdv = 0;
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wire ir_14_17_0 = 0;
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wire ir14_17_eq_0 = ir[14:17] == 0;
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/* ACCP V MEM AC */
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wire accp = 0;
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@ -416,14 +518,14 @@ module apr(
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wire boole_as_01 = 0;
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wire boole_as_10 = 0;
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wire boole_as_11 = 0;
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wire boole_00 = 0;
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wire boole_01 = 0;
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wire boole_02 = 0;
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wire boole_03 = 0;
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wire boole_04 = 0;
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wire boole_05 = 0;
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wire boole_06 = 0;
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wire boole_07 = 0;
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wire boole_0 = 0;
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wire boole_1 = 0;
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wire boole_2 = 0;
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wire boole_3 = 0;
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wire boole_4 = 0;
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wire boole_5 = 0;
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wire boole_6 = 0;
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wire boole_7 = 0;
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wire boole_10 = 0;
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wire boole_11 = 0;
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wire boole_12 = 0;
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@ -490,20 +592,16 @@ module apr(
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reg ex_uuo_sync;
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reg ex_pi_sync;
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reg ex_ill_op;
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wire ex_clr;
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wire ex_set = 0;
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wire ex_clr = mr_start | cpa & iobus_datao_clear;
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wire ex_set = mr_start | cpa & iobus_datao_set;
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wire ex_ir_uuo = 0;
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wire ex_inh_rel = ~ex_user | ex_pi_sync | ma18_31_eq_0 | ex_ill_op;
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pa ex_pa0(.clk(clk), .reset(reset),
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.in(mr_start), // TODO
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.p(ex_clr));
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always @(posedge clk) begin
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if(mr_start) begin
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if(mr_start)
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ex_ill_op <= 0;
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if(mr_start | et7 & jp_jsr & (ex_pi_sync | ex_ill_op))
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ex_user <= 0;
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end
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if(mr_clr) begin
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if(ex_mode_sync)
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ex_user <= 1;
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@ -511,6 +609,10 @@ module apr(
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ex_uuo_sync <= 0;
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ex_pi_sync <= 0;
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end
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if(pi_cyc)
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ex_pi_sync <= 1;
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if(at1)
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ex_uuo_sync <= 1;
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end
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/*
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@ -601,21 +703,19 @@ module apr(
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reg ar_cry0;
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reg ar_cry1;
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wire arlt_clr = ar_clr | at4 | blt_t2 | key_ar_clr;
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wire arlt_cry_initiate = 0;
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wire arlt_com = 0;
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wire arlt_fm_mb_xor = 0;
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wire arlt_fm_mblt0 = 0;
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wire arlt_fm_mblt1 = 0;
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wire arlt_fm_mb_xor = ar_as_t1 | ar_fm_mb_xor;
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wire arlt_fm_mb0 = 0;
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wire arlt_fm_mb1 = 0;
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wire arlt_shlt = 0;
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wire arlt_shrt = 0;
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wire arlt_fm_datasw1 = key_ar_fm_datasw1;
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wire arlt_fm_iob1 = 0;
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wire arrt_clr = ar_clr | key_ar_clr;
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wire arrt_cry_initiate = 0;
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wire arrt_com = 0;
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wire arrt_fm_mb_xor = 0;
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wire arrt_fm_mbrt0 = 0;
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wire arrt_fm_mbrt1 = 0;
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wire arrt_fm_mb_xor = ar_as_t1 | ar_fm_mb_xor;
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wire arrt_fm_mb0 = at0; // TODO
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wire arrt_fm_mb1 = at0; // TODO
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wire arrt_shlt = 0;
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wire arrt_shrt = 0;
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wire arrt_fm_datasw1 = key_ar_fm_datasw1;
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@ -623,6 +723,8 @@ module apr(
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wire ar0_shl_inp = 0;
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wire ar0_shr_inp = 0;
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wire ar35_shl_inp = 0;
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// just one for simplicity
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wire ar_cry_initiate = ar_as_t2;
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wire shc_ashc = 0;
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wire shc_lshc_OR_div = 0;
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@ -642,8 +744,8 @@ module apr(
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wire ar_fm_mb0_et6 = 0;
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wire ar_fm_mb1 = 0;
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wire ar_fm_mb1_et1 = 0;
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wire ar_fm_mb_xor = 0;
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wire ar_fm_mb_xor_et1 = 0;
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wire ar_fm_mb_xor = et1 & ar_fm_mb_xor_et1;
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wire ar_fm_mb_xor_et1 = boole_14 | boole_6 | boole_11 | acbm_com;
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wire ar_fm_mbJ = 0;
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wire ar_fm_mbJ_et0 = 0;
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wire ar_fm_mbltJ_et4 = 0;
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@ -657,16 +759,17 @@ module apr(
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wire ar_incdec_lt_rt = 0;
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wire ar_dec = 0;
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wire ar_sbr = 0;
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wire ar_cry_comp = 0;
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wire ar_cry_comp;
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wire ar_fm_sc1_8J = 0;
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wire ar0_5_fm_sc3_8J = 0;
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wire ar_incdec_t0 = 0;
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wire ar_negate_t0 = 0;
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wire ar_incdec_t1 = 0;
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wire ar_17_cry_in = 0;
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wire ar17_cry_in = 0;
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wire ar_as_t0 = 0;
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wire ar_as_t1 = 0;
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wire ar_as_t2 = 0;
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wire ar_as_t1;
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wire ar_as_t2;
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wire ar_t3;
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wire ar_eq_fp_half = 0;
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wire ar_eq_0 = 0;
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wire ar0_xor_ar1 = 0;
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@ -679,15 +782,75 @@ module apr(
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wire ar_flag_set = 0;
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wire ar_jfcl_clr = 0;
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always @(posedge clk) begin
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pa ar_pa0(); // AR+-1 T0
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pa ar_pa1(); // AR NEGATE T0
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pa ar_pa2(); // AR+-1 T1
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pa ar_pa3(); // AR17 CRY IN
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pa ar_pa4(); // AR AS T0
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pa ar_pa5(.clk(clk), .reset(reset),
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.in(ar_as_t0_D | et3 & ar_add |
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at3 | cfac_ar_add),
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.p(ar_as_t1));
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pa ar_pa6(.clk(clk), .reset(reset),
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.in(ar_as_t1_D),
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.p(ar_as_t2));
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pa ar_pa7(.clk(clk), .reset(reset),
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.in(ar_as_t2 | ar_incdec_t1 | ar17_cry_in),
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.p(ar_cry_comp));
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pa ar_pa8(.clk(clk), .reset(reset),
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.in(ar_cry_comp & ~ar_com_cont |
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ar_cry_comp_D & ar_com_cont),
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.p(ar_t3));
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wire ar_incdec_t0_D, ar_negate_t0_D;
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wire ar_as_t0_D, ar_as_t1_D, ar_cry_comp_D;
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dly100ns ar_dly0(.clk(clk), .reset(reset),
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.in(ar_incdec_t0),
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.p(ar_incdec_t0_D));
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dly100ns ar_dly1(.clk(clk), .reset(reset),
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.in(ar_negate_t0),
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.p(ar_negate_t0_D));
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dly100ns ar_dly2(.clk(clk), .reset(reset),
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.in(ar_as_t0),
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.p(ar_as_t0_D));
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dly100ns ar_dly3(.clk(clk), .reset(reset),
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.in(ar_as_t1),
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.p(ar_as_t1_D));
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dly100ns ar_dly4(.clk(clk), .reset(reset),
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.in(ar_cry_comp),
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.p(ar_cry_comp_D));
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wire [0:35] ar_mb_cry = mb & ~ar;
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always @(posedge clk) begin: arctl
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integer i;
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if(arlt_clr)
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ar[0:17] <= 0;
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if(arrt_clr)
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ar[18:35] <= 0;
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if(ar_cry_initiate)
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ar <= ar + { ar_mb_cry[1:35], 1'b0 };
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if(arlt_fm_mb_xor)
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ar[0:17] <= ar[0:17] ^ mb[0:17];
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if(arrt_fm_mb_xor)
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ar[18:35] <= ar[18:35] ^ mb[18:35];
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for(i = 0; i < 18; i = i+1) begin
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if(arlt_fm_mb0 & ~mb[i])
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ar[i] <= 0;
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if(arlt_fm_mb1 & mb[i])
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ar[i] <= 1;
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if(arrt_fm_mb0 & ~mb[i+18])
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ar[i+18] <= 0;
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if(arrt_fm_mb1 & mb[i+18])
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ar[i+18] <= 1;
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end
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if(arlt_fm_datasw1)
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ar[0:17] <= ar[0:17] | datasw[0:17];
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if(arrt_fm_datasw1)
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ar[18:35] <= ar[18:35] | datasw[18:35];
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if(mr_clr | ar_t3)
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ar_com_cont <= 0;
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end
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/*
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@ -1027,9 +1190,11 @@ module apr(
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wire ma_inc = st6 | key_ma_inc | uuo_t1 |
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ft1a & f_ac_2 |
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it1 & pi_ov;
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wire ma_fm_mbrt1 = 0;
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wire ma_fm_pc1 = 0;
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wire ma_fm_mbrt1 = at5 | ft3 | ft5 |
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et3 & ma_fm_mbrt_et3 | et10 & ma_reset_et9;
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wire ma_fm_pc1 = it1 & ~pi_cyc;
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wire ma31_cry_in_en = ~s_ac_2 & ~f_ac_2;
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wire [30:35] maN_set;
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wire ma_eq_mas = ma == mas;
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wire ma18_31_eq_0 = ma[18:31] == 0;
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@ -1037,9 +1202,17 @@ module apr(
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wire ma_fm_mbrt_et3 = 0;
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wire ma_clr_et1 = 0;
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wire ma_reset_et9 = 0;
|
||||
wire ma_fm_14_17 = 0;
|
||||
wire ma_fm_9_12 = 0;
|
||||
wire ma_fm_pich = 0;
|
||||
wire ma_fm_ir14_17 = at2;
|
||||
wire ma_fm_ir9_12 = 0;
|
||||
wire ma_fm_pich = it1 & pi_cyc;
|
||||
|
||||
assign maN_set[30] = ma_fm_pich | et3 & ex_ir_uuo;
|
||||
assign maN_set[31] = 0;
|
||||
// TODO
|
||||
assign maN_set[32] = pi_enc_32 | ma_fm_ir14_17 & ir[14];
|
||||
assign maN_set[33] = pi_enc_33 | ma_fm_ir14_17 & ir[15];
|
||||
assign maN_set[34] = pi_enc_34 | ma_fm_ir14_17 & ir[16];
|
||||
assign maN_set[35] = ma_fm_ir14_17 & ir[17];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(ma_clr)
|
||||
@ -1048,8 +1221,17 @@ module apr(
|
||||
{ma32_cry_out, ma[32:35]} = ma[32:35]+1;
|
||||
ma[18:31] = ma[18:31] + (ma32_cry_out & ma31_cry_in_en);
|
||||
end
|
||||
if(ma_fm_mbrt1)
|
||||
ma <= ma | mb[18:35];
|
||||
if(ma_fm_pc1)
|
||||
ma <= ma | pc;
|
||||
if(key_ma_fm_masw1)
|
||||
ma <= ma | mas;
|
||||
if(maN_set[30]) ma[30] <= 1;
|
||||
if(maN_set[32]) ma[32] <= 1;
|
||||
if(maN_set[33]) ma[33] <= 1;
|
||||
if(maN_set[34]) ma[34] <= 1;
|
||||
if(maN_set[35]) ma[35] <= 1;
|
||||
end
|
||||
|
||||
/*
|
||||
@ -1091,6 +1273,7 @@ module apr(
|
||||
reg mc_stop;
|
||||
reg mc_stop_sync;
|
||||
reg mc_split_cyc_sync;
|
||||
wire mc_sw_stop = key_mem_stop | sw_addr_stop;
|
||||
wire mc_rd_rq_pulse;
|
||||
wire mc_wr_rq_pulse;
|
||||
wire mc_rdwr_rq_pulse;
|
||||
@ -1233,6 +1416,10 @@ module apr(
|
||||
mc_stop <= 0;
|
||||
if(mc_stop_set)
|
||||
mc_stop <= 1;
|
||||
if(mc_rdwr_rq_pulse)
|
||||
mc_stop_sync <= 1;
|
||||
if(at4 & mc_sw_stop)
|
||||
mc_split_cyc_sync <= 1;
|
||||
end
|
||||
|
||||
/*
|
||||
@ -1264,35 +1451,124 @@ module apr(
|
||||
wire iot_t3a = 0;
|
||||
wire iot_t4 = 0;
|
||||
|
||||
wire iot_t0a_D;
|
||||
dly200ns iot_dly0(.clk(clk), .reset(reset),
|
||||
.in(iot_t0a),
|
||||
.p(iot_t0a_D));
|
||||
|
||||
/* IOB */
|
||||
assign iobus_iob_poweron = 0;
|
||||
assign iobus_iob_reset = 0;
|
||||
assign iobus_datao_clear = 0;
|
||||
assign iobus_datao_set = 0;
|
||||
assign iobus_cono_clear = 0;
|
||||
assign iobus_cono_set = 0;
|
||||
assign iobus_iob_fm_datai = 0;
|
||||
assign iobus_iob_fm_status = 0;
|
||||
assign iobus_iob_out = 0;
|
||||
/*
|
||||
wire [1:7] iobus_pi_req;
|
||||
*/
|
||||
|
||||
/*
|
||||
* PIH, PIR, PIO
|
||||
*/
|
||||
// pih contains the currently serviced pi reqs.
|
||||
// lower channels override higher ones.
|
||||
reg [1:7] pih;
|
||||
wire pih_clr = 0;
|
||||
wire pih_clr = pi_reset;
|
||||
wire pih_fm_pi_ch_rq = 0;
|
||||
wire pih0_fm_pi_ok1 = 0;
|
||||
|
||||
// pir contains all current and allowed pi reqs.
|
||||
reg [1:7] pir;
|
||||
wire pir_clr = 0;
|
||||
wire pir_clr = pi_reset;
|
||||
wire pir_fm_iob1 = 0;
|
||||
wire pir_stb = 0;
|
||||
wire pir_stb;
|
||||
|
||||
// pio is a mask of which pi reqs are allowed.
|
||||
reg [1:7] pio;
|
||||
wire pi_reset = 0;
|
||||
wire pio_fm_iob1 = 0;
|
||||
wire pio0_fm_iob1 = 0;
|
||||
|
||||
// pi_req has the currently highest priority request.
|
||||
wire [1:7] pi_req;
|
||||
// pi_ok is used to mask out low priority reqs
|
||||
wire [1:8] pi_ok;
|
||||
|
||||
// requests coming from the bust
|
||||
wire [1:7] iob_pi_req = iobus_pi_req; // TODO: apr reqs
|
||||
|
||||
genvar i;
|
||||
assign pi_ok[1] = pi_active;
|
||||
for(i = 1; i <= 7; i = i + 1) begin
|
||||
assign pi_req[i] = pi_ok[i] & ~pih[i] & pir[i];
|
||||
assign pi_ok[i+1] = pi_ok[i] & ~pih[i] & ~pir[i];
|
||||
end
|
||||
|
||||
always @(posedge clk) begin: pirctl
|
||||
integer i;
|
||||
if(pih_clr)
|
||||
pih <= 0;
|
||||
if(pir_clr)
|
||||
pir <= 0;
|
||||
if(pir_stb)
|
||||
for(i = 1; i <= 7; i = i+1) begin
|
||||
if(iob_pi_req[i] & pio[i])
|
||||
pir[i] <= 1;
|
||||
end
|
||||
if(pi_reset)
|
||||
pio <= 0;
|
||||
end
|
||||
|
||||
/*
|
||||
* PI
|
||||
*/
|
||||
reg pi_ov;
|
||||
reg pi_cyc;
|
||||
reg pi_active;
|
||||
wire pi_sync = 0;
|
||||
wire pi_rq = 0;
|
||||
wire pi_enc_32 = 0;
|
||||
wire pi_enc_33 = 0;
|
||||
wire pi_enc_34 = 0;
|
||||
wire pi_select = 0;
|
||||
wire pi_status = 0;
|
||||
wire pi_cono_set = 0;
|
||||
wire pi_rq = | pi_req;
|
||||
wire pi_enc_32 = pi_req[4] | pi_req[5] | pi_req[6] | pi_req[7];
|
||||
wire pi_enc_33 = pi_req[2] | pi_req[3] | pi_req[6] | pi_req[7];
|
||||
wire pi_enc_34 = pi_req[1] | pi_req[3] | pi_req[5] | pi_req[7];
|
||||
wire pi_blk_rst = ~pi_ov & iot_datai_o;
|
||||
wire pi_hold = pi_cyc & (~ir_iot | pi_blk_rst);
|
||||
wire pi_rst = (ir_jrst & ir[9]) | (pi_cyc & pi_blk_rst);
|
||||
wire pi_sync;
|
||||
wire pi_reset;
|
||||
|
||||
pa pi_pa0(.clk(clk), .reset(reset),
|
||||
.in(it0 | at0),
|
||||
.p(pi_sync));
|
||||
pa pi_pa1(.clk(clk), .reset(reset),
|
||||
.in(pi_sync & ~pi_cyc | blt_t4),
|
||||
.p(pir_stb));
|
||||
pa pi_pa2(.clk(clk), .reset(reset),
|
||||
.in(mr_start | 1'b0), // TODO
|
||||
.p(pi_reset));
|
||||
|
||||
wire pi_sync_D;
|
||||
dly200ns pi_dly0(.clk(clk), .reset(reset),
|
||||
.in(pi_sync),
|
||||
.p(pi_sync_D));
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(mr_start | et10 & pi_hold) begin
|
||||
pi_ov <= 0;
|
||||
pi_cyc <= 0;
|
||||
end
|
||||
if(iot_t0a & ar_cry0 & pi_cyc)
|
||||
pi_ov <= 1;
|
||||
if(iat0_D0)
|
||||
pi_cyc <= 1;
|
||||
if(pi_reset | pi_cono_set & iobus_iob_in[27])
|
||||
pi_active <= 0;
|
||||
if(pi_cono_set & iobus_iob_in[28])
|
||||
pi_active <= 1;
|
||||
end
|
||||
|
||||
/*
|
||||
* CPA
|
||||
@ -1306,6 +1582,8 @@ module apr(
|
||||
reg cpa_pdl_ov;
|
||||
reg cpa_arov_enable;
|
||||
reg [33:35] cpa_pia;
|
||||
wire cpa = iobus_ios == 0;
|
||||
wire cpa_cono_set = 0;
|
||||
wire cpa_status = 0;
|
||||
|
||||
endmodule
|
||||
|
||||
@ -1,3 +1,15 @@
|
||||
/*module pireq(
|
||||
input wire piok_in,
|
||||
input wire pih,
|
||||
input wire pir,
|
||||
output wire pireq,
|
||||
output wire piok_out
|
||||
);
|
||||
wire a = piok_in & ~pih;
|
||||
assign pireq = a & pir;
|
||||
assign piok_out = a & ~pir;
|
||||
endmodule*/
|
||||
|
||||
module pg(
|
||||
input clk,
|
||||
input reset,
|
||||
@ -22,23 +34,6 @@ module pa(input clk, input reset, input in, output p);
|
||||
p <= in;
|
||||
endmodule
|
||||
|
||||
/*
|
||||
module pa100ns(input clk, input reset, input in, output p);
|
||||
reg [3:0] r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if(reset)
|
||||
r <= 0;
|
||||
else begin
|
||||
if(r)
|
||||
r <= r + 1;
|
||||
if(in)
|
||||
r <= 1;
|
||||
end
|
||||
end
|
||||
assign p = r && r <= 10;
|
||||
endmodule
|
||||
*/
|
||||
|
||||
/* "bus driver", 40ns delayed pulse */
|
||||
module bd(input clk, input reset, input in, output p);
|
||||
reg [2:0] r;
|
||||
@ -207,3 +202,20 @@ module dly100us(input clk, input reset, input in, output p);
|
||||
end
|
||||
assign p = r == 10002;
|
||||
endmodule
|
||||
|
||||
module ldly100us(input clk, input reset, input in, output p, output l);
|
||||
reg [15:0] r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if(reset)
|
||||
r <= 0;
|
||||
else begin
|
||||
if(r)
|
||||
r <= r + 1;
|
||||
if(in)
|
||||
r <= 1;
|
||||
end
|
||||
end
|
||||
assign p = r == 10002;
|
||||
assign l = r != 0 && r < 10002;
|
||||
endmodule
|
||||
|
||||
|
||||
@ -91,7 +91,7 @@ module pdp6(
|
||||
wire [3:9] iobus_ios;
|
||||
wire [0:35] iobus_iob_out;
|
||||
wire [1:7] iobus_pi_req;
|
||||
wire [0:35] iobus_iob_in;
|
||||
wire [0:35] iobus_iob_in = iobus_iob_out;
|
||||
|
||||
|
||||
assign membus_mb_in_p0 = membus_mb_out_p0_p | membus_mb_out_p0_0 | membus_mb_out_p0_1;
|
||||
|
||||
@ -1,15 +1,15 @@
|
||||
[*]
|
||||
[*] GTKWave Analyzer v3.3.76 (w)1999-2016 BSI
|
||||
[*] Sat Nov 12 18:37:06 2016
|
||||
[*] Mon Nov 14 05:59:33 2016
|
||||
[*]
|
||||
[dumpfile] "/home/aap/src/pdp6/verilog/new/dump.vcd"
|
||||
[dumpfile_mtime] "Sat Nov 12 18:36:40 2016"
|
||||
[dumpfile_size] 98790
|
||||
[savefile] "/home/aap/src/pdp6/verilog/new/test.gtkw"
|
||||
[timestart] 0
|
||||
[dumpfile] "/home/aap/src/pdp6/verilog/dump.vcd"
|
||||
[dumpfile_mtime] "Mon Nov 14 05:58:30 2016"
|
||||
[dumpfile_size] 194794
|
||||
[savefile] "/home/aap/src/pdp6/verilog/test.gtkw"
|
||||
[timestart] 6579
|
||||
[size] 1920 1080
|
||||
[pos] -1 -1
|
||||
*-9.650465 1200 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
*-9.885984 8305 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] test.
|
||||
[treeopen] test.pdp6.
|
||||
[treeopen] test.pdp6.mem0.
|
||||
@ -34,7 +34,7 @@ test.pdp6.apr0.sw_art3_maint
|
||||
test.pdp6.apr0.sw_sct_maint
|
||||
@1401200
|
||||
-sw
|
||||
@c00200
|
||||
@800200
|
||||
-keys
|
||||
@28
|
||||
test.pdp6.key_start
|
||||
@ -49,7 +49,7 @@ test.pdp6.key_dep
|
||||
test.pdp6.key_dep_nxt
|
||||
test.pdp6.key_ex
|
||||
test.pdp6.key_ex_nxt
|
||||
@1401200
|
||||
@1000200
|
||||
-keys
|
||||
@800200
|
||||
-regs
|
||||
@ -60,21 +60,23 @@ test.pdp6.apr0.ir[0:17]
|
||||
test.pdp6.apr0.mb[0:35]
|
||||
test.pdp6.apr0.ar[0:35]
|
||||
test.pdp6.apr0.mq[0:35]
|
||||
@31
|
||||
test.pdp6.apr0.datasw[0:35]
|
||||
test.pdp6.apr0.mas[18:35]
|
||||
@1000200
|
||||
-regs
|
||||
@c00200
|
||||
-ex
|
||||
-EX
|
||||
@28
|
||||
test.pdp6.apr0.ex_clr
|
||||
test.pdp6.apr0.ex_user
|
||||
test.pdp6.apr0.ex_mode_sync
|
||||
test.pdp6.apr0.ex_uuo_sync
|
||||
test.pdp6.apr0.ex_pi_sync
|
||||
test.pdp6.apr0.ex_ill_op
|
||||
test.pdp6.apr0.ex_inh_rel
|
||||
@1401200
|
||||
-ex
|
||||
-EX
|
||||
@c00200
|
||||
-key
|
||||
-KEY
|
||||
@28
|
||||
test.pdp6.apr0.run
|
||||
test.pdp6.apr0.key_rim_sbr
|
||||
@ -107,9 +109,9 @@ test.pdp6.apr0.key_rd
|
||||
test.pdp6.apr0.key_wr
|
||||
test.pdp6.apr0.key_rdwr_ret
|
||||
@1401200
|
||||
-key
|
||||
@800200
|
||||
-mc
|
||||
-KEY
|
||||
@c00200
|
||||
-MC
|
||||
@28
|
||||
test.pdp6.apr0.mc_rd_rq_pulse
|
||||
test.pdp6.apr0.mc_rdwr_rq_pulse
|
||||
@ -143,8 +145,63 @@ test.pdp6.apr0.mc_stop
|
||||
test.pdp6.apr0.mc_stop_sync
|
||||
test.pdp6.apr0.mc_split_cyc_sync
|
||||
test.pdp6.apr0.mc_mb_membus_enable
|
||||
@1401200
|
||||
-MC
|
||||
@c00200
|
||||
-I A
|
||||
@28
|
||||
test.pdp6.apr0.it0
|
||||
test.pdp6.apr0.if1a
|
||||
test.pdp6.apr0.it1
|
||||
test.pdp6.apr0.it1a
|
||||
test.pdp6.apr0.at0
|
||||
test.pdp6.apr0.af0
|
||||
test.pdp6.apr0.at1
|
||||
test.pdp6.apr0.at2
|
||||
test.pdp6.apr0.at3
|
||||
test.pdp6.apr0.af3
|
||||
test.pdp6.apr0.at3a
|
||||
test.pdp6.apr0.af3a
|
||||
test.pdp6.apr0.at4
|
||||
test.pdp6.apr0.at5
|
||||
@1401200
|
||||
-I A
|
||||
@800200
|
||||
-F
|
||||
@28
|
||||
test.pdp6.apr0.ft0
|
||||
test.pdp6.apr0.ft1
|
||||
test.pdp6.apr0.ft1a
|
||||
test.pdp6.apr0.ft3
|
||||
test.pdp6.apr0.ft4
|
||||
test.pdp6.apr0.ft4a
|
||||
test.pdp6.apr0.ft5
|
||||
test.pdp6.apr0.ft6
|
||||
test.pdp6.apr0.ft6a
|
||||
@29
|
||||
test.pdp6.apr0.ft7
|
||||
@1000200
|
||||
-mc
|
||||
-F
|
||||
@c00200
|
||||
-iobus
|
||||
@28
|
||||
test.pdp6.apr0.iobus_iob_poweron
|
||||
test.pdp6.apr0.iobus_iob_reset
|
||||
@30
|
||||
test.pdp6.apr0.iobus_pi_req[1:7]
|
||||
test.pdp6.apr0.iobus_ios[3:9]
|
||||
@28
|
||||
test.pdp6.apr0.iobus_cono_clear
|
||||
test.pdp6.apr0.iobus_cono_set
|
||||
test.pdp6.apr0.iobus_datao_clear
|
||||
test.pdp6.apr0.iobus_datao_set
|
||||
test.pdp6.apr0.iobus_iob_fm_datai
|
||||
test.pdp6.apr0.iobus_iob_fm_status
|
||||
@30
|
||||
test.pdp6.apr0.iobus_iob_out[0:35]
|
||||
test.pdp6.apr0.iobus_iob_in[0:35]
|
||||
@1401200
|
||||
-iobus
|
||||
@c00200
|
||||
-membus
|
||||
@28
|
||||
@ -226,5 +283,33 @@ test.pdp6.mem0.cmc_t11
|
||||
test.pdp6.mem0.cmc_t12
|
||||
@1401200
|
||||
-mem0
|
||||
@28
|
||||
test.pdp6.apr0.at1_inh
|
||||
test.pdp6.apr0.ia_NOT_int
|
||||
@800200
|
||||
-PI
|
||||
@30
|
||||
test.pdp6.apr0.maN_set[30:35]
|
||||
@28
|
||||
test.pdp6.apr0.pi_rq
|
||||
test.pdp6.apr0.pi_cyc
|
||||
test.pdp6.apr0.pi_sync
|
||||
test.pdp6.apr0.pir_stb
|
||||
test.pdp6.apr0.pi_req[1:7]
|
||||
test.pdp6.apr0.pih[1:7]
|
||||
test.pdp6.apr0.pir[1:7]
|
||||
test.pdp6.apr0.pio[1:7]
|
||||
test.pdp6.apr0.iob_pi_req[1:7]
|
||||
@1000200
|
||||
-PI
|
||||
@28
|
||||
test.pdp6.apr0.ar_com_cont
|
||||
test.pdp6.apr0.ar_add
|
||||
test.pdp6.apr0.ar_as_t0
|
||||
test.pdp6.apr0.ar_as_t1
|
||||
test.pdp6.apr0.ar_as_t2
|
||||
test.pdp6.apr0.ar_cry_comp
|
||||
test.pdp6.apr0.ar_t3
|
||||
test.pdp6.apr0.cfac_ar_add
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
|
||||
@ -8,10 +8,10 @@ module clock(output reg clk);
|
||||
endmodule
|
||||
|
||||
//`define TESTKEY pdp6.key_inst_stop
|
||||
//`define TESTKEY pdp6.key_read_in
|
||||
`define TESTKEY pdp6.key_read_in
|
||||
//`define TESTKEY pdp6.key_start
|
||||
//`define TESTKEY pdp6.key_exec
|
||||
`define TESTKEY pdp6.key_ex
|
||||
//`define TESTKEY pdp6.key_ex
|
||||
//`define TESTKEY pdp6.key_dep
|
||||
//`define TESTKEY pdp6.key_mem_cont
|
||||
|
||||
@ -24,16 +24,29 @@ module test;
|
||||
|
||||
initial
|
||||
// #110000 $finish;
|
||||
#10000 $finish;
|
||||
#20000 $finish;
|
||||
|
||||
initial begin
|
||||
#100 `TESTKEY = 1;
|
||||
#1000 `TESTKEY = 0;
|
||||
|
||||
// #3000 pdp6.key_dep = 1;
|
||||
// #1000 pdp6.key_dep = 0;
|
||||
// #3000 pdp6.key_dep = 1;
|
||||
// #1000 pdp6.key_dep = 0;
|
||||
|
||||
// #3000 pdp6.key_inst_stop = 1;
|
||||
// #1000 pdp6.key_inst_stop = 0;
|
||||
end
|
||||
|
||||
/*
|
||||
initial begin
|
||||
#400 pdp6.apr0.pio = 7'b1111111;
|
||||
pdp6.apr0.pih = 7'b0000100;
|
||||
pdp6.apr0.pi_active = 1;
|
||||
end
|
||||
assign pdp6.apr0.iobus_pi_req = 7'b0010000;
|
||||
*/
|
||||
assign pdp6.apr0.iobus_pi_req = 0;
|
||||
|
||||
/* initial begin
|
||||
#100;
|
||||
pdp6.mem0_sw_single_step = 1;
|
||||
@ -108,9 +121,10 @@ module test;
|
||||
//pdp6.mas = 18'o777777;
|
||||
|
||||
pdp6.fmem0.ff['o0] = 36'o000000010000;
|
||||
pdp6.fmem0.ff['o4] = 36'o000000010004;
|
||||
pdp6.fmem0.ff['o4] = 36'o000000010304;
|
||||
pdp6.mem0.core['o4] = 36'o222333111666;
|
||||
pdp6.mem0.core['o20] = 36'o777000777000;
|
||||
pdp6.mem0.core['o20] = 36'o200_024_000104;
|
||||
pdp6.mem0.core['o10410] = 36'o000_000_000333;
|
||||
end
|
||||
|
||||
initial begin
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user