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125 lines
4.2 KiB
Markdown
125 lines
4.2 KiB
Markdown
# PDP-6 Emulator and Verilog Simulation
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This project aims to revive the PDP-6 (and later PDP-10)
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computers by DEC.
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I started by writing a very low level emulator in C based on
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the schematics. Later I also wrote an accurate verilog simulation
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that also works on an FPGA.
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Both are driven by a virtual front panel but the plan is to create
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a replica of the original panel.
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The maintenance manual has flow charts, schematics and explanations:
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[Volume1](http://bitsavers.trailing-edge.com/pdf/dec/pdp6/F-67_166instrManVol1_Sep65.pdf)
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[Volume2](http://bitsavers.trailing-edge.com/pdf/dec/pdp6/F-67_166instrManVol2_Sep65.pdf)
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## C Emulator
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The code is more or less a transcription of the schematics into C.
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This means you will not understand it unless you're familiar with the maintenance manual.
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Pulses are represented as functions, when a pulse triggers another pulse
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it does so by the `pulse` function which queues a pulse in a list
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of pulses that are to happen, sorted chronologically.
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Between pulses that happen at different times
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various things are done like checking external pulses and advancing the
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simulation state.
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The timing is not yet 100% accurate but it's pretty close.
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### Building
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The supplied makefile assumes gcc (there are flags to silence some stupid warnings).
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Otherwise you need SDL and pthread.
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### Running
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The cpu (apr), console tty, paper tape and punch,
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the data control and DECtape are implemented.
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340 display is also sort of working.
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The panel is missing the repeat delay knobs,
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but the functionality is implemented.
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## Verilog Simulation
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The verilog code is a very accurate transcription of the schematics as well.
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Since the real machine is asynchronous I had to pull some tricks to make it
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work on an FPGA.
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The real machine uses delays that are triggered by pulses and output another
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pulse after some time. Instead of pulses I use clock enables, and delays are
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implemented by a counter synchronized to the 50MHz system clock.
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### FPGA
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I'm using a DE0-Nano-SoC with has an ARM hps connected to the Cyclone V FPGA.
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On the ARM side runs fe6 (a DDT-like interface) which communicates with
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the FPGA through memory mapped IO registers.
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The quartus project is not yet part of this repo
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but the important modules are in the verilog directory.
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## File tree
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NB: not up to date
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```
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emu the C emulator
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emu/main_panel.c main file for emulator with panel simulation
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emu/main_serial.c main file for emulator with panel over serial line
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emu/emu.c top level emulator code
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emu/cmd.c command line interface
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emu/apr.c Arithmetic Processor 166 emulation
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emu/mem.c core and fast memory emulation
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emu/tty.c Teleprinter 626 emulator
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emu/pt.c Paper tape reader 760 and punch 761 emulation
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emu/dc.c Data Control 136 emulation
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emu/dt.c DECtape 551 and 555 emulation
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emu/netmem.c network protocol for shared memory
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emu/util.c various utility functions
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emu/util.h
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emu/test_*.c test code, not too important anymore
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emu/pdp6.h main header
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emu/args.h argument parsing
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emu/elements.inc panel definition
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emu/cmds.txt command line interface documentation
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emu/init.ini emulator init file
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emu/mem_* core memory backing store
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tools
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tools/dtr2dta.c convert between raw (dtr) and simh (dta) DECtape format
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tools/mkpty.c make a pty and connect to the controlling tty
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tools/mkpty33.c as above but try to pretend an ASR33
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tools/as6.c an assembler, roughly modeled on MACRO
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tools/ld6.c a loader or relocatable files
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tools/pdp6bin.h
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tools/pdp6common.c useful functions for PDP-6 code
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tools/pdp6common.h
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tools/rel.c I have no recollection of this code
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tools/reltest.c old test code to create a REL file
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tools/test.s old test code for the assembler/linker
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tools/test2.s
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tools/ptdump.c print a paper tape file in octal
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tools/dtdump.c print dtr DECtape
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verilog
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verilog/... fpga stuff
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code random code for the PDP-6, mostly testing
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code/bootstrap.txt a list of boot loaders
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code/dtboot.s loads the first block from a DECtape
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code/main.s random entry
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code/tty.s tty character IO
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panel stand alone panel with lots of duplicate code
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art image files for the panel
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misc nothing important
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```
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## To do
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- repeat and maint. switches on panel
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- improve timing
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- do more tests
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- ...
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