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43 lines
745 B
Verilog
Executable File
43 lines
745 B
Verilog
Executable File
module memory_16(
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input wire i_clk,
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input wire i_reset_n,
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input wire [17:0] i_address,
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input wire i_write,
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input wire i_read,
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input wire [35:0] i_writedata,
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output wire [35:0] o_readdata,
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output reg o_waitrequest
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);
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wire addrok = i_address[17:4] == 0;
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wire [3:0] addr = i_address[3:0];
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reg we;
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onchip_ram #(
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.ADDR_WIDTH(4)
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) ram (
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.clk(i_clk),
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.data(i_writedata),
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.addr(addr),
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.we(we),
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.q(o_readdata));
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/* have to wait one clock for ram address */
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always @(posedge i_clk) begin
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if(~i_reset_n) begin
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we <= 0;
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o_waitrequest <= 0;
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end else begin
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if(i_read | i_write)
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o_waitrequest <= 0;
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else
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o_waitrequest <= 1;
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if(we)
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we <= 0;
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else
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we <= i_write & addrok;
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end
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end
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endmodule
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