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aap.pdp6/verilog
History
aap e000f5b5a7 added rim10 format loader
2020-09-03 14:38:22 +02:00
..
tb
lots of additions and changes
2019-12-05 00:31:20 +01:00
apr.v
lots of additions and changes
2019-12-05 00:31:20 +01:00
arbiter.v
fixed emu; new verilog code; fe6 for fpga
2019-10-26 16:49:04 +02:00
clk.v
fixed emu; new verilog code; fe6 for fpga
2019-10-26 16:49:04 +02:00
core32k_x.v
lots of additions and changes
2019-12-05 00:31:20 +01:00
core32k.v
lots of additions and changes
2019-12-05 00:31:20 +01:00
core64k.v
lots of additions and changes
2019-12-05 00:31:20 +01:00
core161c.v
verilog: passing diag part 3
2019-10-29 14:13:52 +01:00
core164.v
fixed emu; new verilog code; fe6 for fpga
2019-10-26 16:49:04 +02:00
core256k_x.v
lots of additions and changes
2019-12-05 00:31:20 +01:00
dis340.v
lots of additions and changes
2019-12-05 00:31:20 +01:00
dly_50.v
lots of additions and changes
2019-12-05 00:31:20 +01:00
fakeapr.v
fixed emu; new verilog code; fe6 for fpga
2019-10-26 16:49:04 +02:00
fast162_dp.v
fixed emu; new verilog code; fe6 for fpga
2019-10-26 16:49:04 +02:00
fast162.v
verilog: passing diag part 3
2019-10-29 14:13:52 +01:00
fe_req.v
fixed emu; new verilog code; fe6 for fpga
2019-10-26 16:49:04 +02:00
gendly6.py
lots of additions and changes
2019-12-05 00:31:20 +01:00
iobus_0_connect.v
KA compatibility
2019-11-04 09:33:03 +01:00
iobus_1_connect.v
KA compatibility
2019-11-04 09:33:03 +01:00
iobus_2_connect.v
KA compatibility
2019-11-04 09:33:03 +01:00
iobus_3_connect.v
KA compatibility
2019-11-04 09:33:03 +01:00
iobus_4_connect.v
lots of additions and changes
2019-12-05 00:31:20 +01:00
iobus_6_connect.v
lots of additions and changes
2019-12-05 00:31:20 +01:00
membus_1_connect.v
KA compatibility
2019-11-04 09:33:03 +01:00
membus_2_connect.v
fixed emu; new verilog code; fe6 for fpga
2019-10-26 16:49:04 +02:00
membus_3_connect.v
fixed emu; new verilog code; fe6 for fpga
2019-10-26 16:49:04 +02:00
membusif.v
fixed emu; new verilog code; fe6 for fpga
2019-10-26 16:49:04 +02:00
memif_d.v
lots of additions and changes
2019-12-05 00:31:20 +01:00
memif.v
fixed emu; new verilog code; fe6 for fpga
2019-10-26 16:49:04 +02:00
memory_16.v
fixed emu; new verilog code; fe6 for fpga
2019-10-26 16:49:04 +02:00
memory_16k.v
fixed emu; new verilog code; fe6 for fpga
2019-10-26 16:49:04 +02:00
memory_32k.v
fixed emu; new verilog code; fe6 for fpga
2019-10-26 16:49:04 +02:00
memory_64k.v
fixed emu; new verilog code; fe6 for fpga
2019-10-26 16:49:04 +02:00
memory_256k_dram.v
lots of additions and changes
2019-12-05 00:31:20 +01:00
memory.v
fixed emu; new verilog code; fe6 for fpga
2019-10-26 16:49:04 +02:00
modules_50.v
verilog: passing diag part 3
2019-10-29 14:13:52 +01:00
onchip_ram.v
fixed emu; new verilog code; fe6 for fpga
2019-10-26 16:49:04 +02:00
panel_6.v
lots of additions and changes
2019-12-05 00:31:20 +01:00
ptp.v
KA compatibility
2019-11-04 09:33:03 +01:00
ptr.v
KA compatibility
2019-11-04 09:33:03 +01:00
testcore161c.v
verilog: passing diag part 3
2019-10-29 14:13:52 +01:00
testfmem.v
fixed emu; new verilog code; fe6 for fpga
2019-10-26 16:49:04 +02:00
testmem16k.v
fixed emu; new verilog code; fe6 for fpga
2019-10-26 16:49:04 +02:00
tty.v
KA compatibility
2019-11-04 09:33:03 +01:00
wcsl420.v
lots of additions and changes
2019-12-05 00:31:20 +01:00
wcsl724.v
lots of additions and changes
2019-12-05 00:31:20 +01:00
wcsl_av.v
lots of additions and changes
2019-12-05 00:31:20 +01:00