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30 lines
615 B
Verilog
30 lines
615 B
Verilog
// AUTOGEN
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module iobus_0_connect(
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// unused
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input wire clk,
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input wire reset,
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// Master
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input wire m_iob_poweron,
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input wire m_iob_reset,
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input wire m_datao_clear,
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input wire m_datao_set,
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input wire m_cono_clear,
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input wire m_cono_set,
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input wire m_iob_fm_datai,
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input wire m_iob_fm_status,
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input wire m_rdi_pulse,
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input wire [3:9] m_ios,
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input wire [0:35] m_iob_write,
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output wire [1:7] m_pi_req,
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output wire [0:35] m_iob_read,
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output wire m_dr_split,
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output wire m_rdi_data
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);
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assign m_pi_req = 0;
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assign m_iob_read = m_iob_write;
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assign m_dr_split = 0;
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assign m_rdi_data = 0;
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endmodule
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