mirror of
https://github.com/aap/pdp6.git
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245 lines
5.4 KiB
Verilog
245 lines
5.4 KiB
Verilog
// UNUSED
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module apr(
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input wire clk,
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input wire reset,
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input wire key_start,
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input wire key_read_in,
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input wire key_inst_cont,
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input wire key_mem_cont,
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input wire key_inst_stop,
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input wire key_mem_stop,
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input wire key_io_reset,
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input wire key_exec,
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input wire key_dep,
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input wire key_dep_nxt,
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input wire key_ex,
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input wire key_ex_nxt,
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input wire sw_repeat,
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input wire sw_addr_stop,
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input wire sw_power,
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input wire sw_mem_disable,
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input wire [0:35] datasw,
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input wire [18:35] mas,
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input wire sw_rim_maint,
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input wire sw_repeat_bypass,
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input wire sw_art3_maint,
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input wire sw_sct_maint,
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input wire sw_split_cyc,
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output reg [0:17] ir,
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output reg [0:35] mi,
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output reg [0:35] ar,
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output reg [0:35] mb,
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output reg [0:35] mq,
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output reg [18:35] pc,
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output reg [18:35] ma,
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output reg run,
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output reg mc_stop,
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output reg pi_active,
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output reg [1:7] pih,
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output reg [1:7] pir,
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output reg [1:7] pio,
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output reg [18:25] pr,
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output reg [18:25] rlr,
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output reg [18:25] rla,
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output wire [0:7] ff0,
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output wire [0:7] ff1,
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output wire [0:7] ff2,
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output wire [0:7] ff3,
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output wire [0:7] ff4,
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output wire [0:7] ff5,
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output wire [0:7] ff6,
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output wire [0:7] ff7,
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output wire [0:7] ff8,
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output wire [0:7] ff9,
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output wire [0:7] ff10,
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output wire [0:7] ff11,
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output wire [0:7] ff12,
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output wire [0:7] ff13,
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// membus
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output wire membus_wr_rs,
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output wire membus_rq_cyc,
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output wire membus_rd_rq,
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output wire membus_wr_rq,
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output wire [21:35] membus_ma,
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output wire [18:21] membus_sel,
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output wire membus_fmc_select,
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output wire [0:35] membus_mb_out,
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input wire membus_addr_ack,
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input wire membus_rd_rs,
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input wire [0:35] membus_mb_in,
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// IO bus
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output wire iobus_iob_poweron,
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output wire iobus_iob_reset,
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output wire iobus_datao_clear,
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output wire iobus_datao_set,
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output wire iobus_cono_clear,
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output wire iobus_cono_set,
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output wire iobus_iob_fm_datai,
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output wire iobus_iob_fm_status,
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output wire [3:9] iobus_ios,
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output wire [0:35] iobus_iob_out,
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input wire [1:7] iobus_pi_req,
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input wire [0:35] iobus_iob_in
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);
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wire key_any = key_start | key_read_in | key_inst_cont | key_mem_cont | key_inst_stop | key_mem_stop | key_ex | key_ex_nxt | key_dep | key_dep_nxt;
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wire key_pulse;
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pg pg0(.clk(clk), .reset(reset),
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.in(key_any),
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.p(key_pulse));
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assign ff1 = 2;
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assign ff2 = 3;
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assign ff3 = 4;
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assign ff4 = 5;
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assign ff5 = 6;
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assign ff6 = 7;
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assign ff7 = 8;
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assign ff8 = 9;
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assign ff9 = 10;
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assign ff10 = 11;
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assign ff11 = 12;
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assign ff12 = 13;
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assign ff13 = 14;
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//initial begin
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// mb <= 36'o111111111111;
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// ar <= 36'o222222222222;
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// mq <= 36'o333333333333;
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// mi <= 36'o444444444444;
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// ir <= 18'o555555;
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// ma <= 18'o666666;
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// pc <= 18'o777777;
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//end
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wire kt0, kt1, kt2;
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wire key_rd, key_wr;
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pa key_pa0(.clk(clk), .reset(reset),
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.in(key_pulse),
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.p(kt0));
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pa key_pa1(.clk(clk), .reset(reset),
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.in(mc_rs_t1 & key_rdwr),
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.p(kt2));
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dly200ns dly0(.clk(clk), .reset(reset),
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.in(kt0),
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.p(kt1));
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dly200ns dly1(.clk(clk), .reset(reset),
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.in(kt1 & (key_ex | key_ex_nxt)),
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.p(key_rd));
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dly200ns dly2(.clk(clk), .reset(reset),
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.in(kt1 & (key_dep | key_dep_nxt)),
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.p(key_wr));
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always @(posedge clk) begin
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if(kt0 & (key_ex | key_dep))
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ma <= 0;
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if(kt0 & (key_ex_nxt | key_dep_nxt))
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ma <= ma + 18'b1;
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if(kt0 & (key_dep | key_dep_nxt))
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ar <= 0;
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if(kt1 & (key_ex | key_dep))
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ma <= ma | mas;
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if(kt1 & (key_dep | key_dep_nxt))
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ar <= ar | datasw;
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if(key_rd | key_wr)
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key_rdwr <= 1;
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if(kt2)
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key_rdwr <= 0;
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end
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assign membus_rq_cyc = mc_rq & (mc_rd | mc_wr);
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assign membus_rd_rq = mc_rd;
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assign membus_wr_rq = mc_wr;
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assign membus_ma = ma[21:35];
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assign membus_sel = 0;
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assign membus_fmc_select = sw_rim_maint;
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assign membus_mb_out = mc_membus_fm_mb1 ? mb : 0;
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wire mai_addr_ack, mai_rd_rs;
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wire mb_pulse;
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pg mc_pg0(.clk(clk), .reset(reset),
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.in(membus_addr_ack), .p(mai_addr_ack));
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pg mc_pg1(.clk(clk), .reset(reset),
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.in(membus_rd_rs), .p(mai_rd_rs));
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pg mc_pg2(.clk(clk), .reset(reset),
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.in(| membus_mb_in),
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.p(mb_pulse));
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wire mc_wr_rs, mc_membus_fm_mb1;
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bd mc_bd0(.clk(clk), .reset(reset), .in(mc_wr_rs), .p(membus_wr_rs));
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bd2 mb_bd1(.clk(clk), .reset(reset), .in(mc_wr_rs), .p(mc_membus_fm_mb1));
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reg key_rdwr = 0;
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reg mc_rd = 0, mc_wr = 0, mc_rq = 0;
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wire mc_addr_ack;
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wire mc_rd_rq_pulse, mc_wr_rq_pulse, mc_rq_pulse;
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wire mc_rs_t0, mc_rs_t1;
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pa mc_pa1(.clk(clk), .reset(reset),
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.in(key_rd),
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.p(mc_rd_rq_pulse));
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pa mc_pa2(.clk(clk), .reset(reset),
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.in(key_wr),
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.p(mc_wr_rq_pulse));
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pa mc_pa3(.clk(clk), .reset(reset),
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.in(mc_rd_rq_pulse | mc_wr_rq_pulse),
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.p(mc_rq_pulse));
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pa mc_pa4(.clk(clk), .reset(reset),
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.in(mai_rd_rs | mc_wr_rs),
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.p(mc_rs_t0));
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pa mc_pa5(.clk(clk), .reset(reset),
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.in(mc_rs_t0),
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.p(mc_rs_t1));
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pa mc_pa6(.clk(clk), .reset(reset),
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.in(mai_addr_ack),
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.p(mc_addr_ack));
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pa mc_pa7(.clk(clk), .reset(reset),
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.in(mc_addr_ack & ~mc_rd & mc_wr),
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.p(mc_wr_rs));
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reg f0 = 0;
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reg f1 = 0;
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always @(posedge clk) begin
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if(mc_rd_rq_pulse) begin
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mc_rd <= 1;
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mc_wr <= 0;
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mb <= 0;
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end
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if(mc_wr_rq_pulse) begin
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mc_rd <= 0;
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mc_wr <= 1;
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end
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if(mc_rq_pulse)
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mc_rq <= 1;
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if(mc_addr_ack)
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mc_rq <= 0;
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if(mai_rd_rs)
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f1 <= 1;
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if(mb_pulse & mc_rd)
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mb <= mb | membus_mb_in;
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if(mc_rs_t1)
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mc_rd <= 0;
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if(key_wr)
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mb <= ar;
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end
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assign ff0 = { 2'b0, f0, f1, key_rdwr, mc_rd, mc_wr, mc_rq };
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endmodule
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