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76 lines
2.8 KiB
Markdown
76 lines
2.8 KiB
Markdown
# PDP-6 Emulator and Verilog Simulation
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This project aims to revive the PDP-6 (and later PDP-10)
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computers by DEC.
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I started by writing a very low level emulator in C based on
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the schematics. Later I also wrote an accurate verilog simulation
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that also works on an FPGA.
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Both are driven by a virtual front panel but the plan is to create
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a replica of the original panel.
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The maintenance manual has flow charts, schematics and explanations:
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[Volume1](http://bitsavers.trailing-edge.com/pdf/dec/pdp6/F-67_166instrManVol1_Sep65.pdf)
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[Volume2](http://bitsavers.trailing-edge.com/pdf/dec/pdp6/F-67_166instrManVol2_Sep65.pdf)
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## C Emulator
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The code is more or less a transcription of the schematics into C.
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This means you will not understand it unless you're familiar with the maintenance manual.
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Pulses are represented as functions, when a pulse triggers another pulse
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it does so by the `nextpulse` function which adds a pulse to the list of next pulses.
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In the main cpu loop the list of current pulses is iterated and each pulse is called,
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then (after checking some external signals) the current and next pulse lists are swapped
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and the process begins anew.
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The timing was not accurately modeled and there is room for improvement.
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Due to the inexact timing the hardware connections (through the memory and IO bus)
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were not implemented too accurately. This may change in the future.
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### Building
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The supplied makefile assumes gcc (there are flags to silence some stupid warnings).
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Otherwise you need SDL and pthread.
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### Running
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The cpu (apr), console tty and paper tape/punch are implemented.
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There are no other external devices yet.
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The only things missing from the cpu is the repeat key mechanism.
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## Verilog Simulation
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The verilog code is a very accurate transcription of the schematics as well.
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Since the real machine is asynchronous I had to pull some tricks to make it
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work on an FPGA.
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The real machine uses delays that are triggered by pulses and output another
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pulse after some time. Instead of pulses I use clock enables, and delays are
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implemented by a counter synchronized to the 100MHz system clock.
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### FPGA
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My FPGA board is a Terasic Cyclone V GX Starter Kit.
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Communication with the virtual front panel is done over I²C via
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GPIO pins 2 (SCL) and 3 (SDA).
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The board's SRAM can also be read and written over I²C.
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The TTY is connected to UART over GPIO pins 4 (RX) and 5 (TX)
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## File tree
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* `emu` source for the emulator
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* `verilog` source for the verilog simulation
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* `art` everything graphical
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* `code` some test code for the PDP-6
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* `panel6` virtual panel for the FPGA
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* `tools` tools like an assembler and linker
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* `misc` some misc. and old stuff
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## To do
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- repeat and maint. switches
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- test thoroughly!
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- devices (test UT, implement 340)
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- timing
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