mirror of
https://github.com/aap/pdp6.git
synced 2026-04-25 20:01:26 +00:00
536 lines
13 KiB
Verilog
536 lines
13 KiB
Verilog
`default_nettype none
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`define synthesis
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module fpdpga6(
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input wire clk,
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input wire [9:0] sw,
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input wire [4:0] key,
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output wire [7:0] ledg,
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output wire [9:0] ledr,
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input wire rx,
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output wire tx,
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output wire [17:0] sram_a,
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inout wire [15:0] sram_d,
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output wire sram_ce,
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output wire sram_oe,
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output wire sram_we,
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output wire sram_lb,
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output wire sram_ub,
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input wire scl,
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inout wire sda
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);
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// TODO: figure out what to do with this
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wire reset = ~key[0];
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wire ack;
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reg ack0;
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wire done = ~ack0 & ack;
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wire [6:0] dev;
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wire [7:0] in;
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wire dir;
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wire start, stop;
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// hardcoded devices:
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wire ok = panelok | coreok;
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wire [7:0] out = panelok ? panelout :
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coreok ? coreout : 8'b0;
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i2cslv slv(.clk(clk), .reset(reset),
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.scl(scl), .sda(sda),
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.dev(dev), .ok(ok),
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.ack(ack), .dir(dir),
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.in(in), .out(out),
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.start(start), .stop(stop));
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always @(posedge clk)
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ack0 <= ack;
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wire [17:0] core_sram_a;
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wire core_sram_ce;
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wire core_sram_oe;
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wire core_sram_we;
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wire core_sram_lb;
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wire core_sram_ub;
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wire [17:0] i2c_sram_a;
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wire i2c_sram_ce;
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wire i2c_sram_oe;
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wire i2c_sram_we;
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wire i2c_sram_lb;
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wire i2c_sram_ub;
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assign sram_a = core_sram_a | i2c_sram_a;
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assign sram_ce = core_sram_ce & i2c_sram_ce;
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assign sram_oe = core_sram_oe & i2c_sram_oe;
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assign sram_we = core_sram_we & i2c_sram_we;
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assign sram_lb = core_sram_lb & i2c_sram_lb;
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assign sram_ub = core_sram_ub & i2c_sram_ub;
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// i2cdev core
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wire coreok = dev == 7'h21;
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wire [7:0] coreout;
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i2c_core i2c_core0(.clk(clk), .reset(reset),
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.start(start), .stop(stop),
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.dir(dir),
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.ok(coreok),
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.done(done),
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.in(in),
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.out(coreout),
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.sram_a(i2c_sram_a),
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.sram_d(sram_d),
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.sram_ce(i2c_sram_ce),
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.sram_oe(i2c_sram_oe),
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.sram_we(i2c_sram_we),
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.sram_lb(i2c_sram_lb),
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.sram_ub(i2c_sram_ub));
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// i2cdev panel
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wire panelok = dev == 7'h26;
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reg [1:0] state;
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reg [7:0] addr;
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reg [7:0] panelout;
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always @(posedge clk) if(panelok) begin
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if(start)
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state <= 0;
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if(stop && dir == 1)
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addr <= addr - 8'b1; // needed for consecutive reads
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if(dir == 0) begin // WRITE
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if(done) begin
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case(state)
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0: begin // got device address
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state <= 1;
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end
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1: begin // got write address
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state <= 2;
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addr <= in;
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end
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2: begin
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case(addr)
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'h0: mas[18:25] <= in;
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'h1: mas[26:33] <= in;
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'h2: mas[34:35] <= in[7:6];
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'h3: datasw[0:7] <= in;
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'h4: datasw[8:15] <= in;
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'h5: datasw[16:23] <= in;
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'h6: datasw[24:31] <= in;
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'h7: datasw[32:35] <= in[7:4];
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'h8: { sw_repeat, sw_addr_stop,
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sw_power, sw_mem_disable } <= in[7:4];
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'h9: { sw_rim_maint, sw_repeat_bypass, sw_art3_maint,
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sw_sct_maint, sw_split_cyc } <= in[7:3];
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'hA: { key_start,
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key_inst_cont,
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key_inst_stop,
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key_io_reset,
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key_dep,
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key_ex,
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key_reader_off,
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key_punch_feed } <= in;
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'hB: { key_read_in,
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key_mem_cont,
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key_mem_stop,
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key_exec,
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key_dep_nxt,
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key_ex_nxt,
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key_reader_on,
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key_reader_feed } <= in;
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endcase
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addr <= addr + 8'b1;
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end
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endcase
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end
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end else if(dir == 1) begin
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if(done) begin
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if(sw_power)
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case(addr)
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8'h0: panelout <= ir[0:7];
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8'h1: panelout <= ir[8:15];
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8'h2: panelout <= { ir[16:17], 6'b0 };
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8'h3: panelout <= pc[18:25];
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8'h4: panelout <= pc[26:33];
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8'h5: panelout <= { pc[34:35], 6'b0 };
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8'h6: panelout <= mi[0:7];
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8'h7: panelout <= mi[8:15];
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8'h8: panelout <= mi[16:23];
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8'h9: panelout <= mi[24:31];
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8'hA: panelout <= { mi[32:35], 4'b0 };
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8'hB: panelout <= ma[18:25];
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8'hC: panelout <= ma[26:33];
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8'hD: panelout <= { ma[34:35], 6'b0 };
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8'hE: panelout <= { run, pih };
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8'hF: panelout <= { mc_stop, pir };
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8'h10: panelout <= { pi_active, pio };
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8'h11: panelout <= { sw_repeat, sw_addr_stop,
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sw_power, sw_mem_disable, 4'b0 };
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8'h12: panelout <= mb[0:7];
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8'h13: panelout <= mb[8:15];
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8'h14: panelout <= mb[16:23];
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8'h15: panelout <= mb[24:31];
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8'h16: panelout <= { mb[32:35], 4'b0 };
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8'h17: panelout <= ar[0:7];
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8'h18: panelout <= ar[8:15];
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8'h19: panelout <= ar[16:23];
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8'h1A: panelout <= ar[24:31];
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8'h1B: panelout <= { ar[32:35], 4'b0 };
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8'h1C: panelout <= mq[0:7];
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8'h1D: panelout <= mq[8:15];
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8'h1E: panelout <= mq[16:23];
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8'h1F: panelout <= mq[24:31];
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8'h20: panelout <= { mq[32:35], 4'b0 };
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8'h21: panelout <= ff[0];
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8'h22: panelout <= ff[1];
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8'h23: panelout <= ff[2];
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8'h24: panelout <= ff[3];
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8'h25: panelout <= ff[4];
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8'h26: panelout <= ff[5];
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8'h27: panelout <= ff[6];
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8'h28: panelout <= ff[7];
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8'h29: panelout <= ff[8];
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8'h2A: panelout <= ff[9];
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8'h2B: panelout <= ff[10];
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8'h2C: panelout <= ff[11];
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8'h2D: panelout <= ff[12];
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8'h2E: panelout <= ff[13];
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8'h2F: panelout <= pr;
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8'h30: panelout <= rlr;
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8'h31: panelout <= rla;
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8'h32: panelout <= { 1'b0, tty_ind };
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8'h33: panelout <= tti_ind;
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default: panelout <= 8'hFF;
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endcase
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else
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panelout <= 8'b0;
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addr <= addr + 8'b1;
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end
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end
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end
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// front panel
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reg [0:35] datasw;
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reg [18:35] mas;
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reg sw_repeat, sw_addr_stop;
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reg sw_power, sw_mem_disable;
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reg sw_rim_maint, sw_repeat_bypass;
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reg sw_art3_maint, sw_sct_maint, sw_split_cyc;
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reg key_start, key_read_in;
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reg key_inst_cont, key_mem_cont;
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reg key_inst_stop, key_mem_stop;
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reg key_io_reset, key_exec;
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reg key_dep, key_dep_nxt;
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reg key_ex, key_ex_nxt;
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reg key_reader_off, key_reader_on;
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reg key_punch_feed, key_reader_feed;
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wire [0:17] ir;
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wire [0:35] mi;
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wire [0:35] ar;
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wire [0:35] mb;
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wire [0:35] mq;
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wire [18:35] pc;
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wire [18:35] ma;
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wire run;
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wire mc_stop;
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wire pi_active;
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wire [1:7] pih;
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wire [1:7] pir;
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wire [1:7] pio;
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wire [18:25] pr;
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wire [18:25] rlr;
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wire [18:25] rla;
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wire [0:7] ff[13:0];
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/* Mem bus */
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wire membus_wr_rs_p0;
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wire membus_rq_cyc_p0;
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wire membus_rd_rq_p0;
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wire membus_wr_rq_p0;
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wire [21:35] membus_ma_p0;
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wire [18:21] membus_sel_p0;
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wire membus_fmc_select_p0;
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wire membus_addr_ack_p0;
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wire membus_rd_rs_p0;
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wire [0:35] membus_mb_in_p0;
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/* Out of apr0 */
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wire [0:35] membus_mb_out_p0_p;
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/* Out of fmem0 */
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wire [0:35] membus_mb_out_p0_0;
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wire membus_addr_ack_p0_0;
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wire membus_rd_rs_p0_0;
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/* Out of mem0 */
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wire [0:35] membus_mb_out_p0_1;
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wire membus_addr_ack_p0_1;
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wire membus_rd_rs_p0_1;
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/* IO bus */
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wire iobus_iob_poweron;
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wire iobus_iob_reset;
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wire iobus_datao_clear;
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wire iobus_datao_set;
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wire iobus_cono_clear;
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wire iobus_cono_set;
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wire iobus_iob_fm_datai;
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wire iobus_iob_fm_status;
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wire [3:9] iobus_ios;
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wire [1:7] iobus_pi_req = tty_pi_req;
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wire [0:35] iobus_iob_in = apr_iob_out | tty_iob_out;
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wire [0:35] apr_iob_out;
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assign membus_mb_in_p0 = membus_mb_out_p0_p | membus_mb_out_p0_0 | membus_mb_out_p0_1;
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assign membus_addr_ack_p0 = membus_addr_ack_p0_0 | membus_addr_ack_p0_1;
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assign membus_rd_rs_p0 = membus_rd_rs_p0_0 | membus_rd_rs_p0_1;
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apr apr0(
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.clk(clk),
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.reset(reset),
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.key_start(key_start),
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.key_read_in(key_read_in),
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.key_inst_cont(key_inst_cont),
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.key_mem_cont(key_mem_cont),
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.key_inst_stop(key_inst_stop),
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.key_mem_stop(key_mem_stop),
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.key_io_reset(key_io_reset),
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.key_exec(key_exec),
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.key_dep(key_dep),
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.key_dep_nxt(key_dep_nxt),
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.key_ex(key_ex),
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.key_ex_nxt(key_ex_nxt),
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.sw_repeat(sw_repeat),
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.sw_addr_stop(sw_addr_stop),
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.sw_power(sw_power),
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.sw_mem_disable(sw_mem_disable),
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.datasw(datasw),
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.mas(mas),
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.sw_rim_maint(sw_rim_maint),
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.sw_repeat_bypass(sw_repeat_bypass),
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.sw_art3_maint(sw_art3_maint),
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.sw_sct_maint(sw_sct_maint),
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.sw_split_cyc(sw_split_cyc),
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.ir(ir),
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.mi(mi),
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.ar(ar),
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.mb(mb),
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.mq(mq),
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.pc(pc),
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.ma(ma),
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.run(run),
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.mc_stop(mc_stop),
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.pi_active(pi_active),
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.pih(pih),
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.pir(pir),
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.pio(pio),
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.pr(pr),
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.rlr(rlr),
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.rla(rla),
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.ff0(ff[0]),
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.ff1(ff[1]),
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.ff2(ff[2]),
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.ff3(ff[3]),
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.ff4(ff[4]),
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.ff5(ff[5]),
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.ff6(ff[6]),
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.ff7(ff[7]),
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.ff8(ff[8]),
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.ff9(ff[9]),
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.ff10(ff[10]),
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.ff11(ff[11]),
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.ff12(ff[12]),
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.ff13(ff[13]),
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.membus_wr_rs(membus_wr_rs_p0),
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.membus_rq_cyc(membus_rq_cyc_p0),
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.membus_rd_rq(membus_rd_rq_p0),
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.membus_wr_rq(membus_wr_rq_p0),
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.membus_ma(membus_ma_p0),
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.membus_sel(membus_sel_p0),
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.membus_fmc_select(membus_fmc_select_p0),
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.membus_mb_out(membus_mb_out_p0_p),
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.membus_addr_ack(membus_addr_ack_p0),
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.membus_rd_rs(membus_rd_rs_p0),
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.membus_mb_in(membus_mb_in_p0),
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.iobus_iob_poweron(iobus_iob_poweron),
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.iobus_iob_reset(iobus_iob_reset),
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.iobus_datao_clear(iobus_datao_clear),
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.iobus_datao_set(iobus_datao_set),
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.iobus_cono_clear(iobus_cono_clear),
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.iobus_cono_set(iobus_cono_set),
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.iobus_iob_fm_datai(iobus_iob_fm_datai),
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.iobus_iob_fm_status(iobus_iob_fm_status),
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.iobus_ios(iobus_ios),
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.iobus_iob_out(apr_iob_out),
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.iobus_pi_req(iobus_pi_req),
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.iobus_iob_in(iobus_iob_in)
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);
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reg mem0_sw_single_step = 0;
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reg mem0_sw_restart = 0;
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fast162 fmem0(
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.clk(clk),
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.reset(reset),
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.power(sw_power),
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.sw_single_step(mem0_sw_single_step),
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.sw_restart(mem0_sw_restart),
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.membus_wr_rs_p0(membus_wr_rs_p0),
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.membus_rq_cyc_p0(membus_rq_cyc_p0),
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.membus_rd_rq_p0(membus_rd_rq_p0),
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.membus_wr_rq_p0(membus_wr_rq_p0),
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.membus_ma_p0(membus_ma_p0),
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.membus_sel_p0(membus_sel_p0),
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.membus_fmc_select_p0(membus_fmc_select_p0),
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.membus_mb_in_p0(membus_mb_in_p0),
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.membus_addr_ack_p0(membus_addr_ack_p0_0),
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.membus_rd_rs_p0(membus_rd_rs_p0_0),
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.membus_mb_out_p0(membus_mb_out_p0_0),
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.membus_rq_cyc_p1(1'b0),
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.membus_sel_p1(4'b0),
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.membus_fmc_select_p1(1'b0),
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.membus_rq_cyc_p2(1'b0),
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.membus_sel_p2(4'b0),
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.membus_fmc_select_p2(1'b0),
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.membus_rq_cyc_p3(1'b0),
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.membus_sel_p3(4'b0),
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.membus_fmc_select_p3(1'b0)
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);
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core161c mem0(
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.clk(clk),
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.reset(reset),
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.power(sw_power),
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.sw_single_step(mem0_sw_single_step),
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.sw_restart(mem0_sw_restart),
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.membus_wr_rs_p0(membus_wr_rs_p0),
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.membus_rq_cyc_p0(membus_rq_cyc_p0),
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.membus_rd_rq_p0(membus_rd_rq_p0),
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.membus_wr_rq_p0(membus_wr_rq_p0),
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.membus_ma_p0(membus_ma_p0),
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.membus_sel_p0(membus_sel_p0),
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.membus_fmc_select_p0(membus_fmc_select_p0),
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.membus_mb_in_p0(membus_mb_in_p0),
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.membus_addr_ack_p0(membus_addr_ack_p0_1),
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.membus_rd_rs_p0(membus_rd_rs_p0_1),
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.membus_mb_out_p0(membus_mb_out_p0_1),
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.membus_rq_cyc_p1(1'b0),
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.membus_sel_p1(4'b0),
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.membus_fmc_select_p1(1'b0),
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.membus_rq_cyc_p2(1'b0),
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.membus_sel_p2(4'b0),
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.membus_fmc_select_p2(1'b0),
|
|
|
|
.membus_rq_cyc_p3(1'b0),
|
|
.membus_sel_p3(4'b0),
|
|
.membus_fmc_select_p3(1'b0),
|
|
|
|
.sram_a(core_sram_a),
|
|
.sram_d(sram_d),
|
|
.sram_ce(core_sram_ce),
|
|
.sram_oe(core_sram_oe),
|
|
.sram_we(core_sram_we),
|
|
.sram_lb(core_sram_lb),
|
|
.sram_ub(core_sram_ub)
|
|
);
|
|
|
|
wire [7:0] tti_ind;
|
|
wire [6:0] tty_ind;
|
|
|
|
wire [1:7] tty_pi_req;
|
|
wire [0:35] tty_iob_out;
|
|
|
|
tty tty0(
|
|
.clk(clk),
|
|
.rx(rx),
|
|
.tx(tx),
|
|
|
|
.tti_ind(tti_ind),
|
|
.status_ind(tty_ind),
|
|
|
|
.iobus_iob_poweron(iobus_iob_poweron),
|
|
.iobus_iob_reset(iobus_iob_reset),
|
|
.iobus_datao_clear(iobus_datao_clear),
|
|
.iobus_datao_set(iobus_datao_set),
|
|
.iobus_cono_clear(iobus_cono_clear),
|
|
.iobus_cono_set(iobus_cono_set),
|
|
.iobus_iob_fm_datai(iobus_iob_fm_datai),
|
|
.iobus_iob_fm_status(iobus_iob_fm_status),
|
|
.iobus_ios(iobus_ios),
|
|
.iobus_iob_in(iobus_iob_in),
|
|
.iobus_pi_req(tty_pi_req),
|
|
.iobus_iob_out(tty_iob_out)
|
|
);
|
|
|
|
assign ledr = { run, 1'b0, tti_ind };
|
|
assign ledg = { 1'b0, tty_ind };
|
|
/*
|
|
assign ledr[7:0] = sw == 0 ? datasw[0:5] :
|
|
sw == 1 ? datasw[6:11] :
|
|
sw == 2 ? datasw[12:17] :
|
|
sw == 3 ? datasw[18:23] :
|
|
sw == 4 ? datasw[24:29] :
|
|
sw == 5 ? datasw[30:35] :
|
|
sw == 6 ? { 4'b0, sw_repeat, sw_addr_stop, sw_power, sw_mem_disable } :
|
|
sw == 7 ? { key_start, key_inst_cont, key_inst_stop, key_io_reset, key_dep, key_ex, key_reader_off, key_punch_feed } :
|
|
6'b0;
|
|
assign ledg[7:0] = sw == 3 ? { 2'b0, mas[18:23] } :
|
|
sw == 4 ? { 2'b0, mas[24:29] } :
|
|
sw == 5 ? { 2'b0, mas[30:35] } :
|
|
sw == 6 ? { 3'b0, sw_rim_maint, sw_repeat_bypass, sw_art3_maint, sw_sct_maint, sw_split_cyc } :
|
|
sw == 7 ? { key_read_in, key_mem_cont, key_mem_stop, key_exec, key_dep_nxt, key_ex_nxt, key_reader_on, key_reader_feed } :
|
|
6'b0;
|
|
|
|
assign ledr[9:8] = 2'b0;
|
|
|
|
assign ledr[5:0] = sw == 0 ? mb[0:5] :
|
|
sw == 1 ? mb[6:11] :
|
|
sw == 2 ? mb[12:17] :
|
|
sw == 3 ? mb[18:23] :
|
|
sw == 4 ? mb[24:29] :
|
|
sw == 5 ? mb[30:35] :
|
|
sw == 6 ? ar[0:5] :
|
|
sw == 7 ? ar[6:11] :
|
|
sw == 8 ? ar[12:17] :
|
|
sw == 9 ? ar[18:23] :
|
|
sw == 10 ? ar[24:29] :
|
|
sw == 11 ? ar[30:35] :
|
|
sw == 12 ? mq[0:5] :
|
|
sw == 13 ? mq[6:11] :
|
|
sw == 14 ? mq[12:17] :
|
|
sw == 15 ? mq[18:23] :
|
|
sw == 16 ? mq[24:29] :
|
|
sw == 17 ? mq[30:35] : 0;
|
|
assign ledr[9:6] = 0;
|
|
assign ledg = 0;
|
|
*/
|
|
|
|
endmodule
|